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Searched refs:VCS0_VCS1_INTR_MASK (Results 1 – 2 of 2) sorted by relevance

/linux-6.15/drivers/gpu/drm/xe/regs/
H A Dxe_irq_regs.h64 #define VCS0_VCS1_INTR_MASK XE_REG(0x1900a8, XE_REG_OPTION_VF) macro
/linux-6.15/drivers/gpu/drm/xe/
H A Dxe_irq.c191 xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~dmask); in xe_irq_enable_hwe()
515 xe_mmio_write32(mmio, VCS0_VCS1_INTR_MASK, ~0); in gt_irq_reset()