Searched refs:VCO_REF_CLK_RATE (Results 1 – 5 of 5) sorted by relevance
35 #define VCO_REF_CLK_RATE 19200000 macro150 rem = rate % VCO_REF_CLK_RATE; in dsi_pll_28nm_clk_set_rate()154 div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500); in dsi_pll_28nm_clk_set_rate()155 gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500); in dsi_pll_28nm_clk_set_rate()159 div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000); in dsi_pll_28nm_clk_set_rate()160 gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000); in dsi_pll_28nm_clk_set_rate()249 u32 ref_clk = VCO_REF_CLK_RATE; in dsi_pll_28nm_clk_recalc_rate()257 ref_clk += (doubler * VCO_REF_CLK_RATE); in dsi_pll_28nm_clk_recalc_rate()
38 #define VCO_REF_CLK_RATE 19200000 macro173 DBG("vco=%lld ref=%d", pconf->vco_current_rate, VCO_REF_CLK_RATE); in pll_14nm_ssc_calc()176 period = (u32)VCO_REF_CLK_RATE / 1000; in pll_14nm_ssc_calc()185 ref = VCO_REF_CLK_RATE; in pll_14nm_ssc_calc()212 u64 fref = VCO_REF_CLK_RATE; in pll_14nm_dec_frac_calc()255 u64 fref = VCO_REF_CLK_RATE; in pll_14nm_calc_vco_count()546 if (dsi_pll_14nm_vco_recalc_rate(hw, VCO_REF_CLK_RATE) == 0) in dsi_pll_14nm_vco_prepare()547 dsi_pll_14nm_vco_set_rate(hw, pll_14nm->phy->cfg->min_pll_rate, VCO_REF_CLK_RATE); in dsi_pll_14nm_vco_prepare()
40 #define VCO_REF_CLK_RATE 19200000 macro117 u64 fref = VCO_REF_CLK_RATE; in dsi_pll_calc_dec_frac()162 ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 - 1; in dsi_pll_calc_ssc()413 u64 ref_clk = VCO_REF_CLK_RATE; in dsi_pll_10nm_vco_recalc_rate()518 VCO_REF_CLK_RATE); in dsi_10nm_pll_restore_state()
41 #define VCO_REF_CLK_RATE 19200000 macro117 u64 fref = VCO_REF_CLK_RATE; in dsi_pll_calc_dec_frac()183 ssc_per = DIV_ROUND_CLOSEST(VCO_REF_CLK_RATE, config->ssc_freq) / 2 - 1; in dsi_pll_calc_ssc()506 u64 ref_clk = VCO_REF_CLK_RATE; in dsi_pll_7nm_vco_recalc_rate()608 VCO_REF_CLK_RATE); in dsi_7nm_pll_restore_state()
43 #define VCO_REF_CLK_RATE 27000000 macro104 val = VCO_REF_CLK_RATE / 10; in dsi_pll_28nm_clk_set_rate()