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Searched refs:VC4_REG32 (Results 1 – 8 of 8) sorted by relevance

/linux-6.15/drivers/gpu/drm/vc4/
H A Dvc4_v3d.c17 VC4_REG32(V3D_IDENT0),
18 VC4_REG32(V3D_IDENT1),
19 VC4_REG32(V3D_IDENT2),
26 VC4_REG32(V3D_CT0CS),
27 VC4_REG32(V3D_CT1CS),
28 VC4_REG32(V3D_CT0EA),
38 VC4_REG32(V3D_PCS),
39 VC4_REG32(V3D_BFC),
40 VC4_REG32(V3D_RFC),
41 VC4_REG32(V3D_BPCA),
[all …]
H A Dvc4_hvs.c37 VC4_REG32(SCALER_DISPCTRL),
38 VC4_REG32(SCALER_DISPSTAT),
39 VC4_REG32(SCALER_DISPID),
41 VC4_REG32(SCALER_DISPPROF),
43 VC4_REG32(SCALER_DISPEOLN),
105 VC4_REG32(SCALER6_EOLN),
108 VC4_REG32(SCALER6_QOS0),
109 VC4_REG32(SCALER6_PROF0),
110 VC4_REG32(SCALER6_QOS1),
112 VC4_REG32(SCALER6_QOS2),
[all …]
H A Dvc4_vec.c253 VC4_REG32(VEC_REVID),
254 VC4_REG32(VEC_CONFIG0),
255 VC4_REG32(VEC_SCHPH),
258 VC4_REG32(VEC_FREQ3_2),
259 VC4_REG32(VEC_FREQ1_0),
260 VC4_REG32(VEC_CONFIG1),
261 VC4_REG32(VEC_CONFIG2),
266 VC4_REG32(VEC_CONFIG3),
267 VC4_REG32(VEC_STATUS0),
268 VC4_REG32(VEC_MASK0),
[all …]
H A Dvc4_dsi.c666 VC4_REG32(DSI0_CTRL),
667 VC4_REG32(DSI0_STAT),
675 VC4_REG32(DSI0_INT_EN),
676 VC4_REG32(DSI0_PHYC),
677 VC4_REG32(DSI0_HS_CLT0),
687 VC4_REG32(DSI0_ID),
691 VC4_REG32(DSI1_CTRL),
692 VC4_REG32(DSI1_STAT),
700 VC4_REG32(DSI1_INT_EN),
701 VC4_REG32(DSI1_PHYC),
[all …]
H A Dvc4_crtc.c67 VC4_REG32(PV_CONTROL),
68 VC4_REG32(PV_V_CONTROL),
70 VC4_REG32(PV_HORZA),
71 VC4_REG32(PV_HORZB),
72 VC4_REG32(PV_VERTA),
73 VC4_REG32(PV_VERTB),
74 VC4_REG32(PV_VERTA_EVEN),
76 VC4_REG32(PV_INTEN),
77 VC4_REG32(PV_INTSTAT),
78 VC4_REG32(PV_STAT),
[all …]
H A Dvc4_txp.c182 VC4_REG32(TXP_DST_PTR),
183 VC4_REG32(TXP_DST_PITCH),
184 VC4_REG32(TXP_DIM),
185 VC4_REG32(TXP_DST_CTRL),
186 VC4_REG32(TXP_PROGRESS),
H A Dvc4_dpi.c116 VC4_REG32(DPI_C),
117 VC4_REG32(DPI_ID),
H A Dvc4_drv.h669 #define VC4_REG32(reg) { .name = #reg, .offset = reg } macro