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Searched refs:VC4_GET_FIELD (Results 1 – 8 of 8) sorted by relevance

/linux-6.15/drivers/gpu/drm/vc4/
H A Dvc4_v3d.c106 uint32_t nslc = VC4_GET_FIELD(ident1, V3D_IDENT1_NSLC); in vc4_v3d_debugfs_ident()
107 uint32_t tups = VC4_GET_FIELD(ident1, V3D_IDENT1_TUPS); in vc4_v3d_debugfs_ident()
108 uint32_t qups = VC4_GET_FIELD(ident1, V3D_IDENT1_QUPS); in vc4_v3d_debugfs_ident()
111 VC4_GET_FIELD(ident1, V3D_IDENT1_REV)); in vc4_v3d_debugfs_ident()
116 VC4_GET_FIELD(ident1, V3D_IDENT1_NSEM)); in vc4_v3d_debugfs_ident()
H A Dvc4_hvs.c253 dispstat = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(i)), in vc4_hvs_debugfs_dlist()
273 VC4_GET_FIELD(dlist_word, in vc4_hvs_debugfs_dlist()
297 dispstat = VC4_GET_FIELD(HVS_READ(SCALER6_DISPX_STATUS(i)), in vc6_hvs_debugfs_dlist()
307 active_dlist = VC4_GET_FIELD(HVS_READ(SCALER6_DISPX_DL(i)), in vc6_hvs_debugfs_dlist()
322 VC4_GET_FIELD(dlist_word, in vc6_hvs_debugfs_dlist()
494 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), in vc4_hvs_get_fifo_frame_count()
498 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), in vc4_hvs_get_fifo_frame_count()
502 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2), in vc4_hvs_get_fifo_frame_count()
510 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), in vc4_hvs_get_fifo_frame_count()
514 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), in vc4_hvs_get_fifo_frame_count()
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H A Dvc4_validate.c584 uint32_t miplevels = VC4_GET_FIELD(p0, VC4_TEX_P0_MIPLVLS); in reloc_tex()
585 uint32_t width = VC4_GET_FIELD(p1, VC4_TEX_P1_WIDTH); in reloc_tex()
586 uint32_t height = VC4_GET_FIELD(p1, VC4_TEX_P1_HEIGHT); in reloc_tex()
618 if (VC4_GET_FIELD(p2, VC4_TEX_P2_PTYPE) == in reloc_tex()
621 if (VC4_GET_FIELD(p3, VC4_TEX_P2_PTYPE) == in reloc_tex()
636 type = (VC4_GET_FIELD(p0, VC4_TEX_P0_TYPE) | in reloc_tex()
637 (VC4_GET_FIELD(p1, VC4_TEX_P1_TYPE4) << 4)); in reloc_tex()
H A Dvc4_render_cl.c440 uint8_t tiling = VC4_GET_FIELD(surf->bits, in vc4_rcl_surface_setup()
442 uint8_t buffer = VC4_GET_FIELD(surf->bits, in vc4_rcl_surface_setup()
444 uint8_t format = VC4_GET_FIELD(surf->bits, in vc4_rcl_surface_setup()
539 uint8_t tiling = VC4_GET_FIELD(surf->bits, in vc4_rcl_render_config_surface_setup()
541 uint8_t format = VC4_GET_FIELD(surf->bits, in vc4_rcl_render_config_surface_setup()
H A Dvc4_crtc.c95 top = VC4_GET_FIELD(dispbase, SCALER6_DISPX_COB_TOP) & ~3; in vc4_crtc_get_cob_allocation()
96 base = VC4_GET_FIELD(dispbase, SCALER6_DISPX_COB_BASE) & ~3; in vc4_crtc_get_cob_allocation()
99 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3; in vc4_crtc_get_cob_allocation()
100 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3; in vc4_crtc_get_cob_allocation()
148 *vpos = VC4_GET_FIELD(val, SCALER6_DISPX_STATUS_YLINE); in vc4_crtc_get_scanout_position()
150 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE); in vc4_crtc_get_scanout_position()
582 encoder_sel = VC4_GET_FIELD(CRTC_READ(PV_CONTROL), PV_CONTROL_CLK_SELECT); in vc4_crtc_disable_at_boot()
836 current_dlist = VC4_GET_FIELD(HVS_READ(SCALER6_DISPX_DL(chan)), in vc4_crtc_handle_page_flip()
H A Dvc4_dsi.c1304 u32 rxlen = VC4_GET_FIELD(rxpkt1h, in vc4_dsi_host_transfer()
1319 msg_rx[0] = VC4_GET_FIELD(rxpkt1h, in vc4_dsi_host_transfer()
1322 msg_rx[1] = VC4_GET_FIELD(rxpkt1h, in vc4_dsi_host_transfer()
H A Dvc4_kms.c276 VC4_GET_FIELD(HVS_READ(SCALER_DISPCTRL), in vc5_hvs_pv_muxing_commit()
H A Dvc4_regs.h20 #define VC4_GET_FIELD(word, field) FIELD_GET(field##_MASK, word) macro