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Searched refs:VC3_PLL1_M_DIV (Results 1 – 1 of 1) sorted by relevance

/linux-6.15/drivers/clk/
H A Dclk-versaclock3.c37 #define VC3_PLL1_M_DIV(n) ((n) & GENMASK(5, 0)) macro
264 mdiv = VC3_PLL1_M_DIV(prediv); in vc3_pfd_recalc_rate()
343 div = VC3_PLL1_M_DIV(idiv); in vc3_pfd_set_rate()