Home
last modified time | relevance | path

Searched refs:UVD_STATUS__IDLE (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_1.c874 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v5_0_1_stop()
1046 ret &= (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v5_0_1_is_idle()
1064 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, UVD_STATUS__IDLE, in vcn_v5_0_1_wait_for_idle()
1065 UVD_STATUS__IDLE); in vcn_v5_0_1_wait_for_idle()
1092 if (RREG32_SOC15(VCN, GET_INST(VCN, i), regUVD_STATUS) != UVD_STATUS__IDLE) in vcn_v5_0_1_set_clockgating_state()
H A Dvcn_v5_0_0.c1011 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v5_0_0_stop()
1240 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v5_0_0_is_idle()
1262 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, in vcn_v5_0_0_wait_for_idle()
1263 UVD_STATUS__IDLE); in vcn_v5_0_0_wait_for_idle()
1293 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) in vcn_v5_0_0_set_clockgating_state()
H A Dvcn_v4_0_5.c1276 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v4_0_5_stop()
1515 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v4_0_5_is_idle()
1537 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, in vcn_v4_0_5_wait_for_idle()
1538 UVD_STATUS__IDLE); in vcn_v4_0_5_wait_for_idle()
1568 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) in vcn_v4_0_5_set_clockgating_state()
H A Dvcn_v1_0.c926 if (status & UVD_STATUS__IDLE) in vcn_v1_0_start_spg_mode()
931 if (status & UVD_STATUS__IDLE) in vcn_v1_0_start_spg_mode()
1180 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v1_0_stop_spg_mode()
1403 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v1_0_is_idle()
1411 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v1_0_wait_for_idle()
1412 UVD_STATUS__IDLE); in vcn_v1_0_wait_for_idle()
H A Dvcn_v4_0_3.c1389 UVD_STATUS__IDLE, 0x7); in vcn_v4_0_3_stop()
1631 UVD_STATUS__IDLE); in vcn_v4_0_3_is_idle()
1651 UVD_STATUS__IDLE, UVD_STATUS__IDLE); in vcn_v4_0_3_wait_for_idle()
1678 regUVD_STATUS) != UVD_STATUS__IDLE) in vcn_v4_0_3_set_clockgating_state()
H A Dvcn_v4_0.c1616 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v4_0_stop()
2021 ret &= (RREG32_SOC15(VCN, i, regUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v4_0_is_idle()
2043 ret = SOC15_WAIT_ON_RREG(VCN, i, regUVD_STATUS, UVD_STATUS__IDLE, in vcn_v4_0_wait_for_idle()
2044 UVD_STATUS__IDLE); in vcn_v4_0_wait_for_idle()
2074 if (RREG32_SOC15(VCN, i, regUVD_STATUS) != UVD_STATUS__IDLE) in vcn_v4_0_set_clockgating_state()
H A Dvcn_v3_0.c1624 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v3_0_stop()
2156 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v3_0_is_idle()
2171 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v3_0_wait_for_idle()
2172 UVD_STATUS__IDLE); in vcn_v3_0_wait_for_idle()
2193 if (RREG32_SOC15(VCN, i, mmUVD_STATUS) != UVD_STATUS__IDLE) in vcn_v3_0_set_clockgating_state()
H A Damdgpu_vcn.h258 UVD_STATUS__IDLE = 0x2, enumerator
H A Dvcn_v2_0.c1203 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_0_stop()
1341 return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_0_is_idle()
1349 ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_0_wait_for_idle()
1350 UVD_STATUS__IDLE); in vcn_v2_0_wait_for_idle()
H A Dvcn_v2_5.c1591 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v2_5_stop()
1935 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS) == UVD_STATUS__IDLE); in vcn_v2_5_is_idle()
1949 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, in vcn_v2_5_wait_for_idle()
1950 UVD_STATUS__IDLE); in vcn_v2_5_wait_for_idle()