| /linux-6.15/Documentation/devicetree/bindings/serial/ |
| H A D | mvebu-uart.txt | 1 * Marvell UART : Non standard UART used in some of Marvell EBU SoCs
6 - "marvell,armada-3700-uart" for the standard variant of the UART
10 UART (128 bytes FIFO, DMA, front interrupts, 8-bit or 32-bit
13 - clocks: UART reference clock used to derive the baudrate. If no clock
18 for standard variant of UART and UART2-clk for extended variant
19 of UART. TBG clock (with UART TBG divisors d1=d2=1) or xtal clock
24 respectively the UART sum interrupt, the UART TX interrupt and
25 UART RX interrupt. A corresponding interrupt-names property must
29 respectively the UART TX interrupt and the UART RX interrupt. A
33 containing only the UART sum interrupt. This form is deprecated
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| H A D | serial.yaml | 18 Each enabled UART may have an optional "serialN" alias in the "aliases" node,
32 the UART's CTS line.
38 the UART's DCD line.
44 the UART's DSR line.
50 the UART's DTR line.
56 the UART's RNG line.
62 the UART's RTS line.
67 The presence of this property indicates that the UART has dedicated lines
70 UART hardware and the board wiring.
98 Serial attached devices shall be a child node of the host UART device
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| H A D | amlogic,meson-uart.yaml | 8 title: Amlogic Meson SoC UART Serial Interface
14 The Amlogic Meson SoC UART Serial Interface is present on a large range
28 - description: Always-on power domain UART controller
38 - description: Always-on power domain UART controller on G12A SoCs
43 - description: Everything-Else power domain UART controller
51 - description: Everything-Else power domain UART controller on G12A SoCs
55 - description: UART controller on S4 compatible SoCs
81 description: The fifo size supported by the UART channel.
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| H A D | cirrus,clps711x-uart.txt | 1 * Cirrus Logic CLPS711X Universal Asynchronous Receiver/Transmitter (UART)
6 - interrupts: Should contain UART TX and RX interrupt.
7 - clocks: Should contain UART core clock number.
8 - syscon: Phandle to SYSCON node, which contain UART control bits.
14 Note: Each UART port should have an alias correctly numbered
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| H A D | nvidia,tegra194-tcu.yaml | 7 title: NVIDIA Tegra Combined UART (TCU)
14 The TCU is a system for sharing a hardware UART instance among multiple
16 based protocol where each "virtual UART" has a pair of mailboxes, one
40 transmitting data from and to the hardware UART.
42 - description: mailbox for receiving data from hardware UART
43 - description: mailbox for transmitting data to hardware UART
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| H A D | arc-uart.txt | 1 * Synopsys ARC UART : Non standard UART used in some of the ARC FPGA boards
7 - clock-frequency : the input clock frequency for the UART
8 - current-speed : baud rate for UART
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| H A D | renesas,em-uart.yaml | 7 title: Renesas EMMA Mobile UART Interface
18 - const: renesas,em-uart # generic EMMA Mobile compatible UART
21 - const: renesas,em-uart # generic EMMA Mobile compatible UART
32 - description: UART functional clock
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| H A D | arm,mps2-uart.txt | 1 ARM MPS2 UART
6 - interrupts : Reference to the UART RX, TX and overrun interrupts
9 - clocks : The input clock of the UART
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| H A D | sifive-serial.yaml | 7 title: SiFive asynchronous serial interface (UART)
28 for the UART as integrated on a particular chip,
29 and "sifive,uart<version>" for the general UART IP
32 UART HDL that corresponds to the IP block version
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| H A D | sprd-uart.yaml | 8 title: Spreadtrum serial UART
45 "enable" for UART module enable clock, "uart" for UART clock, "source"
46 for UART source (parent) clock.
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| /linux-6.15/arch/arm/mach-sa1100/include/mach/ |
| H A D | uncompress.h | 21 #define UART(x) (*(volatile unsigned long *)(serial_port + (x))) macro
29 if (UART(UTCR3) & UTCR3_TXE) break; in putc()
31 if (UART(UTCR3) & UTCR3_TXE) break; in putc()
33 if (UART(UTCR3) & UTCR3_TXE) break; in putc()
38 while (!(UART(UTSR1) & UTSR1_TNF)) in putc()
42 UART(UTDR) = c; in putc()
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| /linux-6.15/Documentation/devicetree/bindings/clock/ |
| H A D | marvell,armada-3700-uart-clock.yaml | 6 title: Marvell Armada 3720 UART clocks
17 - description: UART Clock Control Register
18 - description: UART 2 Baud Rate Divisor Register
22 List of parent clocks suitable for UART from following set:
24 UART clock can use one from this set and when more are provided
28 used for UART (most probably xtal) for smooth boot log on UART.
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| /linux-6.15/Documentation/devicetree/bindings/dma/ |
| H A D | mediatek,uart-dma.yaml | 7 title: MediaTek UART APDMA controller
13 The MediaTek UART APDMA controller provides DMA capabilities
14 for the UART peripheral bus.
38 TX, RX interrupt lines for each UART APDMA channel
52 The first cell specifies the UART APDMA channel number
56 Number of virtual channels of the UART APDMA controller
61 description: Enable 33-bits UART APDMA support
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| /linux-6.15/arch/arm/ |
| H A D | Kconfig.debug | 371 on HI3620 UART.
387 on HIP01 UART.
395 on HIP04 UART.
403 on Hix5hd2 UART.
406 bool "i.MX1 Debug UART"
413 bool "i.MX23 Debug UART"
421 bool "i.MX25 Debug UART"
428 bool "i.MX27 Debug UART"
1065 on SD5203 UART.
1227 are UART A/B/C/D/E.
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| /linux-6.15/arch/arm/include/debug/ |
| H A D | tegra.S | 85 cmp \rv, #2 @ 2 and 3 mean DCC, UART
89 11: lsr \rv, \rp, #15 @ 17:15 are UART ID
91 cmp \rv, #0 @ UART 0?
93 cmp \rv, #1 @ UART 1?
95 cmp \rv, #2 @ UART 2?
97 cmp \rv, #3 @ UART 3?
99 cmp \rv, #4 @ UART 4?
141 cmp \rp, #0 @ Valid UART address?
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| /linux-6.15/Documentation/ABI/testing/ |
| H A D | sysfs-platform-kim | 6 Name of the UART device at which the WL128x chip
21 UART configurations, so the baud-rate needs to be set
32 entry most often should be 1, the host's UART is required
42 use of the shared UART transport, it registers to the shared
46 daemon managing the UART, and is notified about the change
47 by the sysfs_notify. The value would be '1' when UART needs
48 to be opened/ldisc installed, and would be '0' when UART
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| H A D | sysfs-bus-i2c-devices-fsa9480 | 10 UART UART is attached
23 UART switch to UART path
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| /linux-6.15/Documentation/w1/masters/ |
| H A D | w1-uart.rst | 13 UART 1-Wire bus driver. The driver utilizes the UART interface via the
15 the document `"Using a UART to Implement a 1-Wire Bus Master"`_.
17 .. _"Using a UART to Implement a 1-Wire Bus Master": https://www.analog.com/en/technical-articles/u…
19 In short, the UART peripheral must support full-duplex and operate in
26 UART (least significant bit first, start-bit low) sets the reset low time
45 Specify the UART 1-wire bus in the device tree by adding the single child
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| /linux-6.15/Documentation/devicetree/bindings/net/bluetooth/ |
| H A D | mediatek,bluetooth.txt | 1 MediaTek UART based Bluetooth Devices
4 This device is a serial attached device to UART device and thus it must be a
5 child node of the serial node with UART.
22 - pinctrl-0: Should contain UART RXD low when the device is powered up to
24 - pinctrl-1: Should contain UART mode pin ctrl
30 - boot-gpios: GPIO same to the pin as UART RXD and used to keep LOW when
33 - pinctrl-0: Should contain UART mode pin ctrl
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| /linux-6.15/tools/arch/x86/dell-uart-backlight-emulator/ |
| H A D | README | 1 Emulator for DELL0501 UART attached backlight controller
5 board connected to an UART.
12 With the DELL0501 indicating that we are dealing with an UART with
20 1. A (desktop) PC with a 16550 UART on the motherboard and a standard DB9
21 connector connected to this UART.
25 4. A DSDT overlay for the desktop PC replacing the _HID of the 16550 UART
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| /linux-6.15/Documentation/devicetree/bindings/soc/fsl/cpm_qe/qe/ |
| H A D | ucc.txt | 15 - port-number : for UART drivers, the port number to use, between 0 and 3.
18 CPM UART driver, the port-number is required for the QE UART driver.
19 - soft-uart : for UART drivers, if specified this means the QE UART device
20 driver should use "Soft-UART" mode, which is needed on some SOCs that have
21 broken UART hardware. Soft-UART is provided via a microcode upload.
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| /linux-6.15/drivers/tty/serial/ |
| H A D | Kconfig | 962 tristate "SiFive UART support"
968 contains a SiFive UART IP block. This type of UART is present on
972 bool "Console on SiFive UART"
998 bool "Console on Lantiq UART"
1124 tristate "Altera UART support"
1187 UART (AUART) port.
1246 bool "MPS2 UART port"
1260 bool "Console on ARC UART"
1268 int "Number of ARC UART ports"
1534 tristate "Sunplus UART support"
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| /linux-6.15/Documentation/devicetree/bindings/net/ |
| H A D | qca,qca7000.txt | 4 be configured either as SPI or UART slave. This configuration is done by
58 (b) Ethernet over UART
60 In order to use the QCA7000 as UART slave it must be defined as a child of a
61 UART master in the device tree. It is possible to preconfigure the UART
73 UART Example:
75 /* Freescale i.MX28 UART */
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| /linux-6.15/drivers/pinctrl/ |
| H A D | pinctrl-th1520.c | 183 TH1520_PAD(17, AOGPIO_8, UART, AUD, IR, GPIO, ____, ____, 0),
184 TH1520_PAD(18, AOGPIO_9, UART, AUD, IR, GPIO, ____, ____, 0),
220 TH1520_PAD(4, QSPI1_D2_WP, QSPI, ISO, UART, GPIO, FUSE, ____, 0),
221 TH1520_PAD(5, QSPI1_D3_HOLD, QSPI, ISO, UART, GPIO, ____, ____, 0),
226 TH1520_PAD(10, UART1_TXD, UART, ____, ____, GPIO, ____, ____, 0),
227 TH1520_PAD(11, UART1_RXD, UART, ____, ____, GPIO, ____, ____, 0),
228 TH1520_PAD(12, UART4_TXD, UART, ____, ____, GPIO, ____, ____, 0),
229 TH1520_PAD(13, UART4_RXD, UART, ____, ____, GPIO, ____, ____, 0),
230 TH1520_PAD(14, UART4_CTSN, UART, ____, ____, GPIO, ____, ____, 0),
231 TH1520_PAD(15, UART4_RTSN, UART, ____, ____, GPIO, ____, ____, 0),
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| /linux-6.15/Documentation/devicetree/bindings/soc/samsung/ |
| H A D | exynos-usi.yaml | 19 I2C1, SPI, UART, High-Speed I2C0 and I2C1 or both High-Speed
20 I2C1 and UART.
22 In USIv2, only one protocol can be active at a time, either UART, SPI, or
88 manual, it should be set in case of SPI/I2C slave, UART Rx and I2C
90 to "UART".
101 description: Child node describing underlying UART/serial
131 - description: Operating clock for UART/SPI/I2C protocol
158 - description: Operating clock for UART/SPI protocol
181 samsung,clkreq-on; /* needed for UART mode */
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