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Searched refs:TRANSCODER_A (Results 1 – 17 of 17) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Ddisplay.c208 for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) { in emulate_monitor_status_change()
213 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= in emulate_monitor_status_change()
273 vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e; in emulate_monitor_status_change()
327 TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= in emulate_monitor_status_change()
358 TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= in emulate_monitor_status_change()
422 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= in emulate_monitor_status_change()
425 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= in emulate_monitor_status_change()
448 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= in emulate_monitor_status_change()
451 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= in emulate_monitor_status_change()
474 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= in emulate_monitor_status_change()
[all …]
H A Dhandlers.c664 port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) & in vgpu_update_refresh_rate()
680 link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)); in vgpu_update_refresh_rate()
681 link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)); in vgpu_update_refresh_rate()
684 htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(display, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT); in vgpu_update_refresh_rate()
685 vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(display, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT); in vgpu_update_refresh_rate()
2288 MMIO_DH(TRANSCONF(display, TRANSCODER_A), D_ALL, NULL, in init_generic_mmio_info()
/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_display_device.c111 [TRANSCODER_A] = PIPE_A_OFFSET, \
114 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
119 [TRANSCODER_A] = PIPE_A_OFFSET, \
123 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
129 [TRANSCODER_A] = PIPE_A_OFFSET, \
134 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
141 [TRANSCODER_A] = PIPE_A_OFFSET, \
155 [TRANSCODER_A] = PIPE_A_OFFSET, \
240 BIT(TRANSCODER_A) | BIT(TRANSCODER_B)
878 [TRANSCODER_A] = PIPE_A_OFFSET, \
[all …]
H A Dintel_cmtg.c116 cmtg_config->trans_a_secondary = intel_cmtg_transcoder_is_secondary(display, TRANSCODER_A); in intel_cmtg_get_config()
136 intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_A), in intel_cmtg_disable()
H A Dintel_display_limits.h34 TRANSCODER_A = PIPE_A, enumerator
H A Dintel_display_reg_defs.h43 DISPLAY_INFO(display)->trans_offsets[TRANSCODER_A] + \
H A Dintel_display_power.h126 (enum intel_display_power_domain)((tran) - TRANSCODER_A + POWER_DOMAIN_TRANSCODER_A))
H A Dintel_psr_regs.h73 0 : ((trans) - TRANSCODER_A + 1) * 8)
H A Dintel_display.h71 case TRANSCODER_A: in transcoder_name()
H A Dintel_dp_hdcp.c27 case TRANSCODER_A: in transcoder_to_stream_enc_status()
H A Dintel_vdsc.c31 if (DISPLAY_VER(display) == 11 && cpu_transcoder == TRANSCODER_A) in intel_dsc_source_support()
H A Dintel_display_irq.c2010 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | in gen11_display_irq_reset()
2214 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | in gen8_de_irq_postinstall()
H A Dintel_hdcp.c441 case TRANSCODER_A: in intel_hdcp_get_repeater_ctl()
2294 case TRANSCODER_A ... TRANSCODER_D: in intel_get_hdcp_transcoder()
H A Dintel_ddi.c3384 [PORT_B] = TRANSCODER_A, in gen9_chicken_trans_reg_by_port()
3387 [PORT_E] = TRANSCODER_A, in gen9_chicken_trans_reg_by_port()
3940 u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | in bdw_get_trans_port_sync_config()
H A Dintel_psr.c1109 return cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B; in transcoder_has_psr2()
1111 return cpu_transcoder == TRANSCODER_A; in transcoder_has_psr2()
/linux-6.15/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c136 MMIO_D(TRANSCONF(dev_priv, TRANSCODER_A)); in iterate_generic_mmio()
237 MMIO_D(TRANS_HTOTAL(dev_priv, TRANSCODER_A)); in iterate_generic_mmio()
238 MMIO_D(TRANS_HBLANK(dev_priv, TRANSCODER_A)); in iterate_generic_mmio()
239 MMIO_D(TRANS_HSYNC(dev_priv, TRANSCODER_A)); in iterate_generic_mmio()
240 MMIO_D(TRANS_VTOTAL(dev_priv, TRANSCODER_A)); in iterate_generic_mmio()
241 MMIO_D(TRANS_VBLANK(dev_priv, TRANSCODER_A)); in iterate_generic_mmio()
242 MMIO_D(TRANS_VSYNC(dev_priv, TRANSCODER_A)); in iterate_generic_mmio()
243 MMIO_D(BCLRPAT(dev_priv, TRANSCODER_A)); in iterate_generic_mmio()
245 MMIO_D(PIPESRC(dev_priv, TRANSCODER_A)); in iterate_generic_mmio()
498 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A)); in iterate_generic_mmio()
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H A Di915_reg.h2439 #define DP_MST_DPT_DPTP_ALIGN_WA(trans) REG_BIT(9 + (trans) - TRANSCODER_A)
2440 #define DP_MST_SHORT_HBLANK_WA(trans) REG_BIT(5 + (trans) - TRANSCODER_A)
2441 #define DP_MST_FEC_BS_JITTER_WA(trans) REG_BIT(0 + (trans) - TRANSCODER_A)
2478 [TRANSCODER_A] = _CHICKEN_TRANS_A, \