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Searched refs:TIME_STAMP_INT_ENABLE (Results 1 – 16 of 16) sorted by relevance

/linux-6.15/drivers/gpu/drm/radeon/
H A Dcik.c7071 cp_m1p0 |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7074 cp_m1p1 |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7077 cp_m1p2 |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7080 cp_m1p2 |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7089 cp_m2p0 |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7092 cp_m2p1 |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7095 cp_m2p2 |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7098 cp_m2p2 |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7114 cp_m1p0 |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7117 cp_m1p1 |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
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H A Dcikd.h1337 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
1369 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dnid.h497 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Devergreen.c4524 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4528 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4532 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4538 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
H A Dsid.h1282 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dsi.c6063 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6067 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6071 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; in si_irq_set()
H A Devergreend.h1250 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dr600d.h718 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dr600.c3822 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in r600_irq_set()
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dsid.h1153 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dgfx_v12_0.c4649 TIME_STAMP_INT_ENABLE, 0); in gfx_v12_0_set_gfx_eop_interrupt_state()
4657 TIME_STAMP_INT_ENABLE, 1); in gfx_v12_0_set_gfx_eop_interrupt_state()
4700 TIME_STAMP_INT_ENABLE, 0); in gfx_v12_0_set_compute_eop_interrupt_state()
4708 TIME_STAMP_INT_ENABLE, 1); in gfx_v12_0_set_compute_eop_interrupt_state()
H A Dgfx_v11_0.c6190 TIME_STAMP_INT_ENABLE, 0); in gfx_v11_0_set_gfx_eop_interrupt_state()
6198 TIME_STAMP_INT_ENABLE, 1); in gfx_v11_0_set_gfx_eop_interrupt_state()
6247 TIME_STAMP_INT_ENABLE, 0); in gfx_v11_0_set_compute_eop_interrupt_state()
6255 TIME_STAMP_INT_ENABLE, 1); in gfx_v11_0_set_compute_eop_interrupt_state()
H A Dgfx_v9_4_3.c3056 TIME_STAMP_INT_ENABLE, 0); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
3062 TIME_STAMP_INT_ENABLE, 1); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
H A Dgfx_v9_0.c5960 TIME_STAMP_INT_ENABLE, in gfx_v9_0_set_gfx_eop_interrupt_state()
6007 TIME_STAMP_INT_ENABLE, 0); in gfx_v9_0_set_compute_eop_interrupt_state()
6013 TIME_STAMP_INT_ENABLE, 1); in gfx_v9_0_set_compute_eop_interrupt_state()
H A Dgfx_v10_0.c9058 TIME_STAMP_INT_ENABLE, 0); in gfx_v10_0_set_gfx_eop_interrupt_state()
9064 TIME_STAMP_INT_ENABLE, 1); in gfx_v10_0_set_gfx_eop_interrupt_state()
9111 TIME_STAMP_INT_ENABLE, 0); in gfx_v10_0_set_compute_eop_interrupt_state()
9117 TIME_STAMP_INT_ENABLE, 1); in gfx_v10_0_set_compute_eop_interrupt_state()
H A Dgfx_v8_0.c6411 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE, in gfx_v8_0_set_gfx_eop_interrupt_state()