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Searched refs:TEGRA210_CLK_PLL_P (Results 1 – 5 of 5) sorted by relevance

/linux-6.15/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-vi.yaml205 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
206 <&tegra_car TEGRA210_CLK_PLL_P>,
207 <&tegra_car TEGRA210_CLK_PLL_P>;
H A Dnvidia,tegra20-host1x.yaml424 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
425 <&tegra_car TEGRA210_CLK_PLL_P>,
426 <&tegra_car TEGRA210_CLK_PLL_P>;
/linux-6.15/drivers/clk/tegra/
H A Dclk-tegra210.c2571 { .con_id = "pll_p", .dt_id = TEGRA210_CLK_PLL_P },
3560 { TEGRA210_CLK_SCLK_MUX, TEGRA210_CLK_PLL_P, 0, 1 },
3564 { TEGRA210_CLK_SBC4, TEGRA210_CLK_PLL_P, 12000000, 1 },
3581 { TEGRA210_CLK_I2C1, TEGRA210_CLK_PLL_P, 0, 0 },
3582 { TEGRA210_CLK_I2C2, TEGRA210_CLK_PLL_P, 0, 0 },
3583 { TEGRA210_CLK_I2C3, TEGRA210_CLK_PLL_P, 0, 0 },
3584 { TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 },
3585 { TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 },
3586 { TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 },
3598 { TEGRA210_CLK_HDA, TEGRA210_CLK_PLL_P, 51000000, 0 },
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/linux-6.15/include/dt-bindings/clock/
H A Dtegra210-car.h274 #define TEGRA210_CLK_PLL_P 243 macro
/linux-6.15/arch/arm64/boot/dts/nvidia/
H A Dtegra210.dtsi163 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>,
164 <&tegra_car TEGRA210_CLK_PLL_P>,
165 <&tegra_car TEGRA210_CLK_PLL_P>;
1399 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>;