Home
last modified time | relevance | path

Searched refs:TEGRA210_CLK_PLL_C4_OUT0 (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/include/dt-bindings/clock/
H A Dtegra210-car.h342 #define TEGRA210_CLK_PLL_C4_OUT0 308 macro
/linux-6.15/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-vi.yaml188 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
H A Dnvidia,tegra20-host1x.yaml407 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
/linux-6.15/Documentation/devicetree/bindings/mmc/
H A Dnvidia,tegra20-sdhci.yaml309 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
311 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
/linux-6.15/arch/arm64/boot/dts/nvidia/
H A Dtegra210.dtsi145 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1236 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>,
1238 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1302 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
1303 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>;
/linux-6.15/drivers/clk/tegra/
H A Dclk-tegra210.c2534 [tegra_clk_pll_c4_out0] = { .dt_id = TEGRA210_CLK_PLL_C4_OUT0, .present = true },
2619 { .con_id = "pll_c4_out0", .dt_id = TEGRA210_CLK_PLL_C4_OUT0 },
3373 clks[TEGRA210_CLK_PLL_C4_OUT0] = clk; in tegra210_pll_init()