Home
last modified time | relevance | path

Searched refs:TEGRA210_CLK_PLL_A_OUT0 (Results 1 – 7 of 7) sorted by relevance

/linux-6.15/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra-audio-graph-card.yaml76 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
80 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
82 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
102 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
172 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
H A Dnvidia,tegra210-ahub.yaml140 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
177 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
188 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
H A Dnvidia,tegra210-dmic.yaml94 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
H A Dnvidia,tegra210-i2s.yaml110 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
/linux-6.15/arch/arm64/boot/dts/nvidia/
H A Dtegra210.dtsi1524 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1537 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1550 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1563 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1576 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1644 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1656 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
1668 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
2032 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
2036 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
[all …]
/linux-6.15/include/dt-bindings/clock/
H A Dtegra210-car.h280 #define TEGRA210_CLK_PLL_A_OUT0 249 macro
/linux-6.15/drivers/clk/tegra/
H A Dclk-tegra210.c2462 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA210_CLK_PLL_A_OUT0, .present = true },
2591 { .con_id = "pll_a_out0", .dt_id = TEGRA210_CLK_PLL_A_OUT0 },
3553 { TEGRA210_CLK_PLL_A_OUT0, TEGRA210_CLK_CLK_MAX, 11289600, 0 },
3554 { TEGRA210_CLK_I2S0, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3555 { TEGRA210_CLK_I2S1, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3556 { TEGRA210_CLK_I2S2, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3557 { TEGRA210_CLK_I2S3, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },
3558 { TEGRA210_CLK_I2S4, TEGRA210_CLK_PLL_A_OUT0, 11289600, 0 },