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Searched refs:SynchronizedSurfaces (Results 1 – 3 of 3) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddisplay_mode_vba_util_32.c4305 bool SynchronizedSurfaces[DC__NUM_DPP__MAX][DC__NUM_DPP__MAX]; in dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport() local
4501 SynchronizedSurfaces[i][j] = true; in dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
4503 SynchronizedSurfaces[i][j] = false; in dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
4522 if (!SynchronizedSurfaces[k][SurfaceWithMinActiveFCLKChangeMargin]) { in dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
4561 !SynchronizedSurfaces[LastSurfaceWithoutMargin][k]) { in dml32_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddisplay_mode_core_structs.h1756 dml_bool_t SynchronizedSurfaces[__DML_NUM_PLANES__][__DML_NUM_PLANES__]; member
H A Ddisplay_mode_core.c2984 s->SynchronizedSurfaces[i][j] = true; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
2986 s->SynchronizedSurfaces[i][j] = false; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
2999 …} else if (((s->FCLKChangeSupportNumber == 1) && (p->DRRDisplay[k] || (!s->SynchronizedSurfaces[s-… in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
3030 …s->DRAMClockChangeSupportNumber == 1) && (p->DRRDisplay[k] || !s->SynchronizedSurfaces[s->LastSurf… in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()