Home
last modified time | relevance | path

Searched refs:SR_ARR (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.h231 SR_ARR(DCCG_AUDIO_DTO_SOURCE, id), SR_ARR(DCCG_AUDIO_DTO0_MODULE, id), \
232 SR_ARR(DCCG_AUDIO_DTO0_PHASE, id), SR_ARR(DCCG_AUDIO_DTO1_MODULE, id), \
337 SR_ARR(DIO_LINKA_CNTL, id), SR_ARR(DIO_LINKB_CNTL, id), \
338 SR_ARR(DIO_LINKC_CNTL, id), SR_ARR(DIO_LINKD_CNTL, id), \
339 SR_ARR(DIO_LINKE_CNTL, id), SR_ARR(DIO_LINKF_CNTL, id)
571 SR_ARR(DWB_ENABLE_CLK_CTRL, id), SR_ARR(DWB_MEM_PWR_CTRL, id), \
572 SR_ARR(FC_MODE_CTRL, id), SR_ARR(FC_FLOW_CTRL, id), \
573 SR_ARR(FC_WINDOW_START, id), SR_ARR(FC_WINDOW_SIZE, id), \
574 SR_ARR(FC_SOURCE_SIZE, id), SR_ARR(DWB_UPDATE_CTRL, id), \
575 SR_ARR(DWB_CRC_CTRL, id), SR_ARR(DWB_CRC_MASK_R_G, id), \
[all …]
H A Ddcn32_resource.c119 #define SR_ARR(reg_name, id) \ macro
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.h149 SR_ARR(DIO_LINKA_CNTL, id), \
150 SR_ARR(DIO_LINKB_CNTL, id), \
151 SR_ARR(DIO_LINKC_CNTL, id), \
152 SR_ARR(DIO_LINKD_CNTL, id), \
153 SR_ARR(DIO_LINKE_CNTL, id), \
154 SR_ARR(DIO_LINKF_CNTL, id),\
156 SR_ARR(DIO_CLK_CNTL, id)
293 SR_ARR(GSL_SOURCE_SELECT, inst),\
H A Ddcn35_resource.c135 #define SR_ARR(reg_name, id) \ macro
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.h525 SR_ARR(GSL_SOURCE_SELECT, inst), \
H A Ddcn401_resource.c102 #define SR_ARR(reg_name, id)\ macro
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c120 #define SR_ARR(reg_name, id)\ macro
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c120 #define SR_ARR(reg_name, id) \ macro
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c115 #define SR_ARR(reg_name, id) \ macro