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Searched refs:SRI2_ARR (Results 1 – 8 of 8) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.h669 SRI2_ARR(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst), \
670 SRI2_ARR(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst), \
671 SRI2_ARR(MCIF_WB_BUF_PITCH, MCIF_WB, inst), \
672 SRI2_ARR(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst), \
673 SRI2_ARR(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst), \
674 SRI2_ARR(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst), \
675 SRI2_ARR(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst), \
676 SRI2_ARR(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst), \
677 SRI2_ARR(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst), \
678 SRI2_ARR(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst), \
[all …]
H A Ddcn32_resource.c147 #define SRI2_ARR(reg_name, block, id)\ macro
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.h58 SRI2_ARR(OPP_TOP_CLK_CONTROL, OPP, id)
160 SRI2_ARR(MMHUBBUB_CLOCK_CNTL, MMHUBBUB, inst)
308 SRI2_ARR(OPTC_CLOCK_CONTROL, OPTC, inst),\
H A Ddcn35_resource.c164 #define SRI2_ARR(reg_name, block, id)\ macro
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c148 #define SRI2_ARR(reg_name, block, id)\ macro
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn36/
H A Ddcn36_resource.c149 #define SRI2_ARR(reg_name, block, id)\ macro
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn351/
H A Ddcn351_resource.c144 #define SRI2_ARR(reg_name, block, id)\ macro
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c136 #define SRI2_ARR(reg_name, block, id)\ macro