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Searched refs:SPLL_CTL (Results 1 – 6 of 6) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_pch_refclk.c399 u32 ctl = intel_de_read(dev_priv, SPLL_CTL); in spll_uses_pch_ssc()
H A Dintel_dpll_mgr.c710 intel_de_write(display, SPLL_CTL, hw_state->spll); in hsw_ddi_spll_enable()
711 intel_de_posting_read(display, SPLL_CTL); in hsw_ddi_spll_enable()
738 intel_de_rmw(display, SPLL_CTL, SPLL_PLL_ENABLE, 0); in hsw_ddi_spll_disable()
739 intel_de_posting_read(display, SPLL_CTL); in hsw_ddi_spll_disable()
784 val = intel_de_read(display, SPLL_CTL); in hsw_ddi_spll_get_hw_state()
H A Dintel_display_power.c1188 intel_de_read(display, SPLL_CTL) & SPLL_PLL_ENABLE, in assert_can_disable_lcpll()
/linux-6.15/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c490 MMIO_D(SPLL_CTL); in iterate_generic_mmio()
H A Di915_reg.h3688 #define SPLL_CTL _MMIO(0x46020) macro
/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c486 switch (vgpu_vreg_t(vgpu, SPLL_CTL) & SPLL_FREQ_MASK) { in bdw_vgpu_get_dp_bitrate()
498 vgpu->id, port_name(port), vgpu_vreg_t(vgpu, SPLL_CTL)); in bdw_vgpu_get_dp_bitrate()