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Searched refs:SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK (Results 1 – 14 of 14) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_2_sh_mask.h8837 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x1f macro
H A Dgfx_8_0_sh_mask.h10447 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x7f macro
H A Dgfx_8_1_sh_mask.h10845 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK 0x7f macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h12295 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK … macro
H A Dgc_9_1_sh_mask.h13675 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK … macro
H A Dgc_9_2_1_sh_mask.h13471 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK … macro
H A Dgc_9_4_3_sh_mask.h15822 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK … macro
H A Dgc_9_4_2_sh_mask.h24905 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK … macro
H A Dgc_11_5_0_sh_mask.h13877 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK … macro
H A Dgc_11_0_0_sh_mask.h17183 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK … macro
H A Dgc_12_0_0_sh_mask.h27206 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK … macro
H A Dgc_10_1_0_sh_mask.h19676 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK … macro
H A Dgc_11_0_3_sh_mask.h19426 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK … macro
H A Dgc_10_3_0_sh_mask.h18037 #define SPI_WCL_PIPE_PERCENT_HP3D__VALUE_MASK … macro