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Searched refs:SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7484 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x00000040L macro
H A Dgfx_7_2_sh_mask.h9251 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40 macro
H A Dgfx_8_0_sh_mask.h10971 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40 macro
H A Dgfx_8_1_sh_mask.h11369 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK 0x40 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h20383 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK … macro
H A Dgc_9_1_sh_mask.h21690 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK … macro
H A Dgc_9_2_1_sh_mask.h21620 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK … macro
H A Dgc_9_4_3_sh_mask.h23742 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK … macro
H A Dgc_9_4_2_sh_mask.h13818 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK … macro
H A Dgc_11_5_0_sh_mask.h23747 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK … macro
H A Dgc_11_0_0_sh_mask.h27709 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK … macro
H A Dgc_12_0_0_sh_mask.h33813 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK … macro
H A Dgc_10_1_0_sh_mask.h8493 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK … macro
H A Dgc_11_0_3_sh_mask.h30232 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK … macro
H A Dgc_10_3_0_sh_mask.h8835 #define SPI_CONFIG_CNTL_1__PC_LIMIT_ENABLE_MASK … macro