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Searched refs:SOC15_WAIT_ON_RREG (Results 1 – 19 of 19) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_0.c558 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, in vcn_v5_0_0_disable_static_power_gating()
563 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v5_0_0_disable_static_power_gating()
569 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v5_0_0_disable_static_power_gating()
575 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v5_0_0_disable_static_power_gating()
581 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, in vcn_v5_0_0_disable_static_power_gating()
586 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, 0, in vcn_v5_0_0_disable_static_power_gating()
632 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v5_0_0_enable_static_power_gating()
638 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v5_0_0_enable_static_power_gating()
644 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v5_0_0_enable_static_power_gating()
650 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v5_0_0_enable_static_power_gating()
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H A Dvcn_v4_0_5.c587 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
592 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
597 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
603 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
607 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
611 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
615 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_disable_static_power_gating()
649 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_enable_static_power_gating()
654 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_enable_static_power_gating()
659 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_IPX_DLDO_STATUS, in vcn_v4_0_5_enable_static_power_gating()
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H A Dvcn_v1_0.c1186 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v1_0_stop_spg_mode()
1195 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v1_0_stop_spg_mode()
1228 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, in vcn_v1_0_stop_dpg_mode()
1234 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v1_0_stop_dpg_mode()
1237 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v1_0_stop_dpg_mode()
1245 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, in vcn_v1_0_stop_dpg_mode()
1293 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, in vcn_v1_0_pause_dpg_mode()
1301 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, in vcn_v1_0_pause_dpg_mode()
1323 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, in vcn_v1_0_pause_dpg_mode()
1362 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, in vcn_v1_0_pause_dpg_mode()
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H A Dvcn_v3_0.c691 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, in vcn_v3_0_disable_static_power_gating()
709 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_PGFSM_STATUS, 0, 0x3F3FFFFF); in vcn_v3_0_disable_static_power_gating()
815 SOC15_WAIT_ON_RREG(VCN, inst, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v3_0_disable_clock_gating()
1585 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v3_0_stop_dpg_mode()
1590 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v3_0_stop_dpg_mode()
1598 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v3_0_stop_dpg_mode()
1632 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v3_0_stop()
1642 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v3_0_stop()
1711 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, in vcn_v3_0_pause_dpg_mode()
1753 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, in vcn_v3_0_pause_dpg_mode()
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H A Dvcn_v2_0.c776 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, in vcn_v2_0_disable_static_power_gating()
790 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0, 0xFFFFF); in vcn_v2_0_disable_static_power_gating()
844 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFF); in vcn_v2_0_enable_static_power_gating()
1166 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, in vcn_v2_0_stop_dpg_mode()
1171 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_0_stop_dpg_mode()
1174 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v2_0_stop_dpg_mode()
1179 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1, in vcn_v2_0_stop_dpg_mode()
1211 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_0_stop()
1222 r = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_0_stop()
1285 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE, in vcn_v2_0_pause_dpg_mode()
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H A Dvcn_v4_0.c652 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, in vcn_v4_0_disable_static_power_gating()
738 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_PGFSM_STATUS, data, 0x3F3FFFFF); in vcn_v4_0_enable_static_power_gating()
790 SOC15_WAIT_ON_RREG(VCN, inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v4_0_disable_clock_gating()
1573 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, in vcn_v4_0_stop_dpg_mode()
1578 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v4_0_stop_dpg_mode()
1580 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1, in vcn_v4_0_stop_dpg_mode()
1624 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); in vcn_v4_0_stop()
1634 r = SOC15_WAIT_ON_RREG(VCN, i, regUVD_LMI_STATUS, tmp, tmp); in vcn_v4_0_stop()
1709 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_DPG_PAUSE, in vcn_v4_0_pause_dpg_mode()
1713 SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, in vcn_v4_0_pause_dpg_mode()
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H A Dvcn_v5_0_1.c536 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_DPG_PAUSE, in vcn_v5_0_1_pause_dpg_mode()
836 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, in vcn_v5_0_1_stop_dpg_mode()
841 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v5_0_1_stop_dpg_mode()
874 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, UVD_STATUS__IDLE, 0x7); in vcn_v5_0_1_stop()
882 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); in vcn_v5_0_1_stop()
892 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, tmp); in vcn_v5_0_1_stop()
1064 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, UVD_STATUS__IDLE, in vcn_v5_0_1_wait_for_idle()
H A Dvcn_v2_5.c811 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v2_5_disable_clock_gating()
1552 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1557 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1560 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF); in vcn_v2_5_stop_dpg_mode()
1565 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1, in vcn_v2_5_stop_dpg_mode()
1599 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_5_stop()
1610 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp); in vcn_v2_5_stop()
1673 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE, in vcn_v2_5_pause_dpg_mode()
1707 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, in vcn_v2_5_pause_dpg_mode()
1713 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1, in vcn_v2_5_pause_dpg_mode()
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H A Djpeg_v3_0.c293 r = SOC15_WAIT_ON_RREG(JPEG, 0, in jpeg_v3_0_disable_static_power_gating()
328 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS, in jpeg_v3_0_enable_static_power_gating()
489 return SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, in jpeg_v3_0_wait_for_idle()
H A Djpeg_v4_0_5.c378 SOC15_WAIT_ON_RREG(JPEG, inst, regUVD_IPX_DLDO_STATUS, in jpeg_v4_0_5_disable_static_power_gating()
403 SOC15_WAIT_ON_RREG(JPEG, inst, regUVD_IPX_DLDO_STATUS, in jpeg_v4_0_5_enable_static_power_gating()
434 SOC15_WAIT_ON_RREG(JPEG, inst_idx, regUVD_IPX_DLDO_STATUS, in jpeg_v4_0_5_start_dpg_mode()
676 return SOC15_WAIT_ON_RREG(JPEG, i, regUVD_JRBC_STATUS, in jpeg_v4_0_5_wait_for_idle()
H A Dumsch_mm_v4_0.c67 SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS, in umsch_mm_v4_0_load_microcode()
164 r = SOC15_WAIT_ON_RREG(VCN, 0, regVCN_MES_MSTATUS_LO, 0xAAAAAAAA, 0xFFFFFFFF); in umsch_mm_v4_0_load_microcode()
261 SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS, in umsch_mm_v4_0_ring_stop()
H A Djpeg_v5_0_0.c275 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS, 0, in jpeg_v5_0_0_disable_power_gating()
295 SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_IPX_DLDO_STATUS, in jpeg_v5_0_0_enable_power_gating()
578 return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS, in jpeg_v5_0_0_wait_for_idle()
H A Dvcn_v4_0_3.c666 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_CGC_GATE, 0, 0xFFFFFFFF); in vcn_v4_0_3_disable_clock_gating()
1346 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, in vcn_v4_0_3_stop_dpg_mode()
1351 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_RB_RPTR, tmp, 0xFFFFFFFF); in vcn_v4_0_3_stop_dpg_mode()
1353 SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_POWER_STATUS, 1, in vcn_v4_0_3_stop_dpg_mode()
1388 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_STATUS, in vcn_v4_0_3_stop()
1397 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, in vcn_v4_0_3_stop()
1408 r = SOC15_WAIT_ON_RREG(VCN, vcn_inst, regUVD_LMI_STATUS, tmp, in vcn_v4_0_3_stop()
1650 ret = SOC15_WAIT_ON_RREG(VCN, GET_INST(VCN, i), regUVD_STATUS, in vcn_v4_0_3_wait_for_idle()
H A Djpeg_v2_0.c236 r = SOC15_WAIT_ON_RREG(JPEG, 0, in jpeg_v2_0_disable_power_gating()
267 r = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_PGFSM_STATUS, in jpeg_v2_0_enable_power_gating()
697 ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK, in jpeg_v2_0_wait_for_idle()
H A Djpeg_v4_0.c330 r = SOC15_WAIT_ON_RREG(JPEG, 0, in jpeg_v4_0_disable_static_power_gating()
365 r = SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_PGFSM_STATUS, in jpeg_v4_0_enable_static_power_gating()
649 return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS, in jpeg_v4_0_wait_for_idle()
H A Dvpe_v6_1.c292 ret = SOC15_WAIT_ON_RREG(VPE, i, regVPEC_QUEUE_RESET_REQ_6_1_1, 0, in vpe_v_6_1_ring_stop()
296 ret = SOC15_WAIT_ON_RREG(VPE, i, regVPEC_QUEUE_RESET_REQ, 0, in vpe_v_6_1_ring_stop()
H A Dsoc15_common.h100 #define SOC15_WAIT_ON_RREG(ip, inst, reg, expected_value, mask) \ macro
H A Djpeg_v2_5.c544 ret = SOC15_WAIT_ON_RREG(JPEG, i, mmUVD_JRBC_STATUS, in jpeg_v2_5_wait_for_idle()
H A Djpeg_v4_0_3.c536 SOC15_WAIT_ON_RREG(JPEG, jpeg_inst, regUVD_PGFSM_STATUS, in jpeg_v4_0_3_start_inst()