Searched refs:SMU_DCEFCLK (Results 1 – 10 of 10) sorted by relevance
222 case SMU_DCEFCLK: in renoir_get_dpm_clk_limited()567 case SMU_DCEFCLK: in renoir_print_clk_levels()590 case SMU_DCEFCLK: in renoir_print_clk_levels()
298 SMU_DCEFCLK, enumerator
712 SMU_DCEFCLK, in smu_v13_0_7_set_default_dpm_table()1239 case SMU_DCEFCLK: in smu_v13_0_7_print_clk_levels()1255 case SMU_DCEFCLK: in smu_v13_0_7_print_clk_levels()2065 case SMU_DCEFCLK: in smu_v13_0_7_force_clk_levels()
714 SMU_DCEFCLK, in smu_v13_0_0_set_default_dpm_table()1250 case SMU_DCEFCLK: in smu_v13_0_0_print_clk_levels()1266 case SMU_DCEFCLK: in smu_v13_0_0_print_clk_levels()2076 case SMU_DCEFCLK: in smu_v13_0_0_force_clk_levels()
921 SMU_DCEFCLK); in smu_v13_0_init_max_sustainable_clocks()1090 clk_select = SMU_DCEFCLK; in smu_v13_0_display_clock_voltage_request()
647 SMU_DCEFCLK, in smu_v14_0_2_set_default_dpm_table()1114 case SMU_DCEFCLK: in smu_v14_0_2_print_clk_levels()1130 case SMU_DCEFCLK: in smu_v14_0_2_print_clk_levels()1474 case SMU_DCEFCLK: in smu_v14_0_2_force_clk_levels()
1067 SMU_DCEFCLK, in navi10_set_default_dpm_table()1286 case SMU_DCEFCLK: in navi10_emit_clk_levels()1497 case SMU_DCEFCLK: in navi10_print_clk_levels()1698 case SMU_DCEFCLK: in navi10_force_clk_levels()1809 case SMU_DCEFCLK: in navi10_get_clock_by_type_with_latency()
869 SMU_DCEFCLK); in smu_v11_0_init_max_sustainable_clocks()1066 clk_select = SMU_DCEFCLK; in smu_v11_0_display_clock_voltage_request()
1084 SMU_DCEFCLK, in sienna_cichlid_set_default_dpm_table()1304 case SMU_DCEFCLK: in sienna_cichlid_print_clk_levels()1474 case SMU_DCEFCLK: in sienna_cichlid_force_clk_levels()
2545 clk_type = SMU_DCEFCLK; break; in smu_force_ppclk_levels()2929 clk_type = SMU_DCEFCLK; break; in smu_convert_to_smuclk()3319 clk_type = SMU_DCEFCLK; in smu_get_clock_by_type_with_latency()