Searched refs:SKL_DPLL0 (Results 1 – 2 of 2) sorted by relevance
949 (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | in skl_dpll0_update()950 DPLL_CTRL1_SSC(SKL_DPLL0) | in skl_dpll0_update()951 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) != in skl_dpll0_update()952 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) in skl_dpll0_update()955 switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { in skl_dpll0_update()956 case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): in skl_dpll0_update()967 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); in skl_dpll0_update()1071 DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | in skl_dpll0_enable()1072 DPLL_CTRL1_SSC(SKL_DPLL0) | in skl_dpll0_enable()1073 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0), in skl_dpll0_enable()[all …]
385 #define SKL_DPLL0 0 macro