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Searched refs:SDRAM (Results 1 – 25 of 68) sorted by relevance

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/linux-6.15/arch/arm/mach-pxa/
H A Dsleep.S55 @ prepare SDRAM refresh settings
59 @ enable SDRAM self-refresh mode
96 @ prepare SDRAM refresh settings
100 @ enable SDRAM self-refresh mode
107 @ We keep the change-down close to the actual suspend on SDRAM
160 @ external accesses after SDRAM is put in self-refresh mode
166 @ put SDRAM into self-refresh
/linux-6.15/Documentation/devicetree/bindings/arm/altera/
H A Dsocfpga-sdram-edac.txt1 Altera SOCFPGA SDRAM Error Detection & Correction [EDAC]
2 The EDAC accesses a range of registers in the SDRAM controller.
7 - interrupts : Should contain the SDRAM ECC IRQ in the
/linux-6.15/Documentation/driver-api/memory-devices/
H A Dti-emif.rst4 TI EMIF SDRAM Controller Driver
29 SoCs. EMIF is an SDRAM controller that, based on its revision,
30 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
/linux-6.15/Documentation/devicetree/bindings/arm/omap/
H A Ddmm.txt4 SDRAM controllers (called EMIFs on OMAP). DMM manages various aspects of memory
5 accesses such as priority generation amongst initiators, configuration of SDRAM
/linux-6.15/Documentation/devicetree/bindings/memory-controllers/ti/
H A Demif.txt1 * EMIF family of TI SDRAM controllers
3 EMIF - External Memory Interface - is an SDRAM controller used in
57 has capability for generating SDRAM temperature alerts
/linux-6.15/drivers/video/fbdev/omap/
H A DKconfig42 bool "Set DMA SDRAM access priority high"
46 (SDRAM) this will speed up graphics DMA operations.
/linux-6.15/arch/arm/boot/dts/renesas/
H A Dr7s9210-rza2mevb.dts8 * Hence the 64 MiB of SDRAM on the sub-board needs to be enabled, which has
22 * SW6 SW6-1 set to SDRAM
78 reg = <0x0c000000 0x04000000>; /* SDRAM */
/linux-6.15/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr-props.yaml48 Density in megabits of SDRAM chip. Decoded from Mode Register 8.
68 IO bus width in bits of SDRAM chip. Decoded from Mode Register 8.
H A Djedec,lpddr2.yaml7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
37 Revision 1 value of SDRAM chip. Obtained from device datasheet.
45 Revision 2 value of SDRAM chip. Obtained from device datasheet.
H A Djedec,lpddr4.yaml7 title: LPDDR4 SDRAM compliant to JEDEC JESD209-4
H A Djedec,lpddr5.yaml7 title: LPDDR5 SDRAM compliant to JEDEC JESD209-5
/linux-6.15/Documentation/devicetree/bindings/memory-controllers/
H A Dmediatek,mt7621-memc.yaml7 title: MT7621 SDRAM controller
H A Dmarvell,mvebu-sdram-controller.yaml7 title: Marvell MVEBU SDRAM controller
H A Dsamsung,s5pv210-dmc.yaml13 Dynamic Memory Controller interfaces external JEDEC DDR-type SDRAM.
/linux-6.15/Documentation/devicetree/bindings/fpga/
H A Daltr,socfpga-fpga2sdram-bridge.yaml7 title: Altera FPGA To SDRAM Bridge
/linux-6.15/arch/arm/mach-lpc32xx/
H A Dsuspend.S50 @ Wait for SDRAM busy status to go busy and then idle
/linux-6.15/Documentation/arch/arm/stm32/
H A Dstm32f429-overview.rst13 - External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
H A Dstm32mp151-overview.rst19 - FMC controller to connect SDRAM, NOR and NAND memories
H A Dstm32h743-overview.rst13 - FMC controller to connect SDRAM, NOR and NAND memories
H A Dstm32mp13-overview.rst19 - FMC controller to connect SDRAM, NOR and NAND memories
H A Dstm32h750-overview.rst13 - FMC controller to connect SDRAM, NOR and NAND memories
H A Dstm32f746-overview.rst13 - FMC controller to connect SDRAM, NOR and NAND memories
H A Dstm32f769-overview.rst13 - FMC controller to connect SDRAM, NOR and NAND memories
/linux-6.15/arch/arm/mach-omap1/
H A Dsleep.S86 @ prepare to put SDRAM into self-refresh manually
156 @ Prepare to put SDRAM into self-refresh manually
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dmvebu-core-clock.txt30 3 = hclk (SDRAM Controller Internal Clock)
31 4 = dclk (SDRAM Interface Clock)

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