| /linux-6.15/include/dt-bindings/clock/ |
| H A D | rk3036-cru.h | 24 #define SCLK_UART1 78 macro
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| H A D | exynos7-clk.h | 96 #define SCLK_UART1 4 macro
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| H A D | s5pv210.h | 196 #define SCLK_UART1 174 macro
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| H A D | rk3188-cru-common.h | 21 #define SCLK_UART1 65 macro
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| H A D | rk3128-cru.h | 26 #define SCLK_UART1 78 macro
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| H A D | rk3228-cru.h | 25 #define SCLK_UART1 78 macro
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| H A D | rk3308-cru.h | 22 #define SCLK_UART1 18 macro
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| H A D | rv1108-cru.h | 23 #define SCLK_UART1 73 macro
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| H A D | rockchip,rk3562-cru.h | 190 #define SCLK_UART1 178 macro
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| H A D | rk3328-cru.h | 28 #define SCLK_UART1 39 macro
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| H A D | rk3288-cru.h | 33 #define SCLK_UART1 78 macro
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| H A D | rk3368-cru.h | 31 #define SCLK_UART1 78 macro
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| H A D | px30-cru.h | 26 #define SCLK_UART1 24 macro
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| H A D | rockchip,rk3528-cru.h | 34 #define SCLK_UART1 22 macro
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| H A D | rockchip,rk3576-cru.h | 513 #define SCLK_UART1 495 macro
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| H A D | rockchip,rv1126-cru.h | 25 #define SCLK_UART1 11 macro
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| H A D | rk3399-cru.h | 39 #define SCLK_UART1 82 macro
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| H A D | rockchip,rk3588-cru.h | 186 #define SCLK_UART1 171 macro
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| H A D | rk3568-cru.h | 351 #define SCLK_UART1 287 macro
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| /linux-6.15/Documentation/devicetree/bindings/clock/ |
| H A D | rockchip,rk3568-cru.yaml | 16 (examples: provide SCLK_UART1\PCLK_UART1 and SRST_P_UART1\SRST_S_UART1 for UART module)
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| /linux-6.15/drivers/clk/rockchip/ |
| H A D | clk-rk3036.c | 154 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3128.c | 190 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3228.c | 204 MUX(SCLK_UART1, "sclk_uart1", mux_uart1_p, CLK_SET_RATE_PARENT,
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| /linux-6.15/drivers/clk/samsung/ |
| H A D | clk-s5pv210.c | 597 GATE(SCLK_UART1, "sclk_uart1", "dout_uart1", CLK_SRC_MASK0, 13,
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| /linux-6.15/arch/arm/boot/dts/rockchip/ |
| H A D | rk3xxx.dtsi | 125 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
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