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/linux-6.15/arch/arc/lib/
H A Dmemcpy-archs.S9 # define SHIFT_1(RX,RY,IMM) asl RX, RY, IMM ; << argument
10 # define SHIFT_2(RX,RY,IMM) lsr RX, RY, IMM ; >> argument
11 # define MERGE_1(RX,RY,IMM) asl RX, RY, IMM argument
13 # define EXTRACT_1(RX,RY,IMM) and RX, RY, 0xFFFF argument
14 # define EXTRACT_2(RX,RY,IMM) lsr RX, RY, IMM argument
16 # define SHIFT_1(RX,RY,IMM) lsr RX, RY, IMM ; >> argument
20 # define EXTRACT_1(RX,RY,IMM) lsr RX, RY, IMM argument
25 # define LOADX(DST,RX) ldd.ab DST, [RX, 8] argument
26 # define STOREX(SRC,RX) std.ab SRC, [RX, 8] argument
30 # define LOADX(DST,RX) ld.ab DST, [RX, 4] argument
[all …]
H A Dmemcpy-archs-unaligned.S12 # define LOADX(DST,RX) ldd.ab DST, [RX, 8] argument
13 # define STOREX(SRC,RX) std.ab SRC, [RX, 8] argument
17 # define LOADX(DST,RX) ld.ab DST, [RX, 4] argument
18 # define STOREX(SRC,RX) st.ab SRC, [RX, 4] argument
/linux-6.15/Documentation/gpu/amdgpu/
H A Ddgpu-asic-info-table.csv13 Radeon (TM) (RX|Pro WX) E9260 /460 /V5300X /550 /560(X) Series, POLARIS11, DCE 11.2, 8, VCE 3.4 / U…
14 Radeon (RX/Pro) 500 /540(X) /550 /640 /WX2100 /WX3100 /WX200 Series, POLARIS12, DCE 11.2, 8, VCE 3.…
15 Radeon (RX|TM) (PRO|WX) Vega /MI25 /V320 /V340L /8200 /9100 /SSG MxGPU, VEGA10, DCE 12, 9.0.1, VCE …
20 AMD Radeon (RX|Pro) 5600(M|XT) /5700 (M|XT|XTB) /W5700, NAVI10, DCN 2.0.0, 10.1.10, VCN 2.0.0, 5.0.0
22 AMD Radeon RX 6800(XT) /6900(XT) /W6800, SIENNA_CICHLID, DCN 3.0.0, 10.3.0, VCN 3.0.0, 5.2.0
23 AMD Radeon RX 6700 XT / 6800M / 6700M, NAVY_FLOUNDER, DCN 3.0.0, 10.3.2, VCN 3.0.0, 5.2.2
24 AMD Radeon RX 6600(XT) /6600M /W6600 /W6600M, DIMGREY_CAVEFISH, DCN 3.0.2, 10.3.4, VCN 3.0.16, 5.2.4
25 AMD Radeon RX 6500M /6300M /W6500M /W6300M, BEIGE_GOBY, DCN 3.0.3, 10.3.5, VCN 3.0.33, 5.2.5
26 AMD Radeon RX 7900 XT /XTX, , DCN 3.2.0, 11.0.0, VCN 4.0.0, 6.0.0
27 AMD Radeon RX 7800 XT, , DCN 3.2.0, 11.0.3, VCN 4.0.0, 6.0.3
[all …]
/linux-6.15/arch/x86/crypto/
H A Dcast5-avx-x86_64-asm_64.S46 #define RX %xmm8 macro
136 vpxor a1, RX, a1; \
247 inpack_blocks(RL1, RR1, RTMP, RX, RKM);
248 inpack_blocks(RL2, RR2, RTMP, RX, RKM);
249 inpack_blocks(RL3, RR3, RTMP, RX, RKM);
250 inpack_blocks(RL4, RR4, RTMP, RX, RKM);
320 inpack_blocks(RL1, RR1, RTMP, RX, RKM);
321 inpack_blocks(RL2, RR2, RTMP, RX, RKM);
465 vmovq (%r12), RX;
466 vpshufd $0x4f, RX, RX;
[all …]
H A Dcast6-avx-x86_64-asm_64.S47 #define RX %xmm8 macro
130 F_head(b1, RX, RGI1, RGI2, op0); \
131 F_head(b2, RX, RGI3, RGI4, op0); \
133 F_tail(b1, RX, RGI1, RGI2, op1, op2, op3); \
136 vpxor a1, RX, a1; \
269 inpack_blocks(RA1, RB1, RC1, RD1, RTMP, RX, RKRF, RKM);
270 inpack_blocks(RA2, RB2, RC2, RD2, RTMP, RX, RKRF, RKM);
293 outunpack_blocks(RA1, RB1, RC1, RD1, RTMP, RX, RKRF, RKM);
294 outunpack_blocks(RA2, RB2, RC2, RD2, RTMP, RX, RKRF, RKM);
317 inpack_blocks(RA1, RB1, RC1, RD1, RTMP, RX, RKRF, RKM);
[all …]
/linux-6.15/Documentation/devicetree/bindings/net/
H A Dmicrel-ksz90x1.txt49 - rxdv-skew-ps : Skew control of RX CTL pad
52 - rxd0-skew-ps : Skew control of RX data 0 pad
53 - rxd1-skew-ps : Skew control of RX data 1 pad
54 - rxd2-skew-ps : Skew control of RX data 2 pad
55 - rxd3-skew-ps : Skew control of RX data 3 pad
137 - rxc-skew-ps : Skew control of RX clock pad
142 - rxdv-skew-ps : Skew control of RX CTL pad
144 - rxd0-skew-ps : Skew control of RX data 0 pad
145 - rxd1-skew-ps : Skew control of RX data 1 pad
146 - rxd2-skew-ps : Skew control of RX data 2 pad
[all …]
H A Dxlnx,axi-ethernet.yaml13 segments of memory for buffering TX and RX, as well as the capability of
14 offloading TX/RX checksum calculation off the processor.
47 present DMA node should contains TX/RX DMA interrupts else DMA interrupt
82 RX checksum offload. 0 or empty for disabling RX checksum offload,
83 1 to enable partial RX checksum offload and 2 to enable full RX
114 from that device (DMA registers and DMA TX/RX interrupts) rather than
129 description: TX and RX DMA channel phandle
/linux-6.15/drivers/spi/
H A Dspi-loopback-test.c97 .rx_buf = RX(0),
135 .rx_buf = RX(0),
202 .rx_buf = RX(0),
219 .rx_buf = RX(0),
236 .rx_buf = RX(0),
250 .rx_buf = RX(0),
278 .rx_buf = RX(0),
293 .rx_buf = RX(0),
311 .rx_buf = RX(0),
319 .rx_buf = RX(0),
[all …]
/linux-6.15/Documentation/networking/device_drivers/can/freescale/
H A Dflexcan.rst13 For most flexcan IP cores the driver supports 2 RX modes:
20 configured for RX-FIFO mode.
22 The RX FIFO mode uses a hardware FIFO with a depth of 6 CAN frames,
40 more performant "RX mailbox" mode and will use "RX FIFO" mode
47 This mode activates the "RX mailbox mode" for better performance, on
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dstarfive,jh7110-syscrg.yaml23 - description: GMAC1 RMII reference or GMAC1 RGMII RX
26 - description: External I2S RX bit clock
27 - description: External I2S RX left/right channel clock
37 - description: GMAC1 RGMII RX
40 - description: External I2S RX bit clock
41 - description: External I2S RX left/right channel clock
H A Dqcom,sa8775p-gcc.yaml26 - description: UFS memory first RX symbol clock
27 - description: UFS memory second RX symbol clock
29 - description: UFS card first RX symbol clock
30 - description: UFS card second RX symbol clock
H A Dstarfive,jh7110-aoncrg.yaml23 - description: GMAC0 RMII reference or GMAC0 RGMII RX
30 - description: GMAC0 RMII reference or GMAC0 RGMII RX
31 - description: STG AXI/AHB or GMAC0 RGMII RX
39 - description: GMAC0 RGMII RX
H A Dqcom,gcc-apq8084.yaml32 - description: UFS RX symbol 0 clock
33 - description: UFS RX symbol 1 clock
37 - description: SATA RX clock
/linux-6.15/drivers/net/ethernet/mellanox/mlx4/
H A Den_cq.c104 if (cq->type == RX) { in mlx4_en_activate_cq()
132 if (cq->type == RX) in mlx4_en_activate_cq()
135 if ((cq->type != RX && priv->hwtstamp_config.tx_type) || in mlx4_en_activate_cq()
136 (cq->type == RX && priv->hwtstamp_config.rx_filter)) in mlx4_en_activate_cq()
157 case RX: in mlx4_en_activate_cq()
187 cq->type == RX) in mlx4_en_destroy_cq()
201 if (cq->type == RX) in mlx4_en_deactivate_cq()
/linux-6.15/Documentation/devicetree/bindings/sound/
H A Dqcom,wcd937x-sdw.yaml14 It has RX and TX Soundwire slave devices. This bindings is for the
49 WCD9370 RX Port 1 (HPH_L/R) <==> SWR1 Port 1 (HPH_L/R)
50 WCD9370 RX Port 2 (CLSH) <==> SWR1 Port 2 (CLSH)
51 WCD9370 RX Port 3 (COMP_L/R) <==> SWR1 Port 3 (COMP_L/R)
52 WCD9370 RX Port 4 (LO) <==> SWR1 Port 4 (LO)
53 WCD9370 RX Port 5 (DSD_L/R) <==> SWR1 Port 5 (DSD)
H A Dnvidia,tegra30-ahub.txt59 For RX CIFs, the numbers indicate the register number within AHUB routing
60 register space (APBIF 0..3 RX, I2S 0..5 RX, DAM 0..2 RX 0..1, SPDIF RX 0..1).
H A Dallwinner,sun4i-a10-i2s.yaml94 - description: RX DMA Channel
98 data. In such a case, the RX DMA channel is to be omitted.
108 data. In such a case, the RX name is to be omitted.
114 - description: RX DMA Channel
/linux-6.15/Documentation/networking/
H A Dmac80211-auth-assoc-deauth.txt32 driver->mac80211: RX probe response
36 driver->mac80211: RX auth frame
40 driver->mac80211: RX auth frame
44 mac80211->userspace: RX auth frame
60 driver->mac80211: RX assoc response
/linux-6.15/Documentation/devicetree/bindings/dma/
H A Dintel,ldma.yaml67 DMA byte enable is only valid for DMA write(RX).
79 Enable RX dynamic burst write. When it is enabled, the DMA does RX dynamic burst;
80 if it is disabled, the DMA RX will still support programmable fixed burst size of 2,4,8,16.
81 It only applies to RX DMA and memcopy DMA.
/linux-6.15/sound/soc/fsl/
H A Dimx-audio-rpmsg.c49 spin_lock_irqsave(&info->lock[RX], flags); in imx_audio_rpmsg_cb()
54 spin_unlock_irqrestore(&info->lock[RX], flags); in imx_audio_rpmsg_cb()
55 info->callback[RX](info->callback_param[RX]); in imx_audio_rpmsg_cb()
H A Dfsl_ssi.c56 #define RX 0 macro
407 int dir = tx ? TX : RX; in fsl_ssi_config_enable()
511 int adir = tx ? RX : TX; in fsl_ssi_config_disable()
512 int dir = tx ? TX : RX; in fsl_ssi_config_disable()
591 vals[RX].srcr = SSI_SRCR_RFEN0; in fsl_ssi_setup_regvals()
599 vals[RX].scr = vals[TX].scr = 0; in fsl_ssi_setup_regvals()
602 vals[RX].srcr |= SSI_SRCR_RFEN1; in fsl_ssi_setup_regvals()
607 vals[RX].sier |= SSI_SIER_RDMAE; in fsl_ssi_setup_regvals()
610 vals[RX].sier |= SSI_SIER_RIE; in fsl_ssi_setup_regvals()
876 vals[RX].srcr |= SSI_SRCR_RFEN1; in fsl_ssi_hw_params()
[all …]
/linux-6.15/Documentation/networking/device_drivers/ethernet/google/
H A Dgve.rst33 - Bar2 - IRQ, RX and TX doorbells
147 - Every TX and RX queue is assigned a notification block.
149 - TX and RX buffers queues, which send descriptors to the device, use MMIO
152 - RX and TX completion queues, which receive descriptors from the device, use a
159 - It's the driver's responsibility to ensure that the RX and TX completion
163 - TX packets have a 16 bit completion_tag and RX buffers have a 16 bit
164 buffer_id. These will be returned on the TX completion and RX queues
174 The driver posts fixed sized buffers to HW on the RX buffer queue. The packet
175 received on the associated RX queue may span multiple descriptors.
/linux-6.15/Documentation/networking/device_drivers/ethernet/amazon/
H A Dena.rst210 .. _`RX copybreak`:
212 RX copybreak
219 This option controls the maximum packet length for which the RX
221 than RX copybreak bytes is received, it is copied into a new memory
222 buffer and the RX descriptor is returned to HW.
334 Dynamic RX Buffers (DRB)
337 Each RX descriptor in the RX ring is a single memory page (which is either 4KB
349 |4KB RX Buffer |
355 HW as an RX buffer of size 4KB - 300Bytes = 3796 Bytes
357 |****|3796 Bytes RX Buffer|
[all …]
/linux-6.15/Documentation/admin-guide/perf/
H A Ddwc_pcie_pmu.rst17 - one 64-bit counter for Time Based Analysis (RX/TX data throughput and
27 Using this feature you can obtain information regarding RX/TX data
76 Example usage of counting PCIe RX TLP data payload (Units of bytes)::
80 The average RX/TX bandwidth can be calculated using the following formula:
82 PCIe RX Bandwidth = rx_pcie_tlp_data_payload / Measure_Time_Window
/linux-6.15/Documentation/devicetree/bindings/media/
H A Dnxp,imx8-isi.yaml17 CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
88 description: MIPI CSI-2 RX
105 description: MIPI CSI-2 RX 0
107 description: MIPI CSI-2 RX 1

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