Home
last modified time | relevance | path

Searched refs:RTS (Results 1 – 25 of 91) sorted by relevance

1234

/linux-6.15/Documentation/devicetree/bindings/leds/
H A Drichtek,rt8515.yaml16 RFS and RTS.
42 description: The resistance value of the RTS resistor. This
44 for the property torch-max-microamp to work, the RTS resistor
71 is hardwired to the component using the RTS resistor to
73 according to the formula Imax = 5500 / RTS. The lowest
77 current below the hardware limit. This requires the RTS
/linux-6.15/Documentation/devicetree/bindings/serial/
H A Drs485.yaml9 description: The RTS signal is capable of automatically controlling line
32 description: drive RTS high when sending (this is the default).
36 description: drive RTS low when sending (default is high).
40 description: Polarity of receiver enable signal (when separate from RTS).
H A Dserial.yaml62 the UART's RTS line.
68 for RTS/CTS hardware flow control, and that they are available for use
78 description: CTS and RTS pins are swapped.
H A Dcirrus,clps711x-uart.txt11 - {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD
/linux-6.15/arch/arm64/boot/dts/freescale/
H A Dimx8mm-phygate-tauri-l-rs232-rts-cts.dtso6 * Tauri-L RS232 with RTS/CTS hardware flow control:
7 * - UART4_TX becomes RTS
H A Dimx8mm-venice-gw72xx-0x-rs232-rts.dtso5 * GW72xx RS232 with RTS/CTS hardware flow control:
7 * - UART4_TX becomes RTS
H A Dimx8mm-venice-gw73xx-0x-rs232-rts.dtso5 * GW73xx RS232 with RTS/CTS hardware flow control:
7 * - UART4_TX becomes RTS
H A Dimx8mp-dhcom-drc02.dts184 * DHCOM UART1 RTS/CTS pins. Therefore this UART have to use DHCOM GPIOs
185 * for RTS/CTS. So configure DHCOM GPIO I as RTS and GPIO M as CTS.
197 * controlled by DHCOM GPIO P. So remove RTS/CTS pins and the property
H A Dimx8mq-hummingboard-pulse.dts166 * reconfigured to enable RTS/CTS on UART3
209 * Header. To use RTS/CTS on UART3 comment them out
/linux-6.15/Documentation/driver-api/serial/
H A Dserial-rs485.rst20 toggling RTS or DTR signals. That can be used to control external
77 /* Set logical level for RTS pin equal to 1 when sending: */
79 /* or, set logical level for RTS pin equal to 0 when sending: */
82 /* Set logical level for RTS pin equal to 1 after sending: */
84 /* or, set logical level for RTS pin equal to 0 after sending: */
/linux-6.15/arch/arm/boot/dts/nxp/imx/
H A Dimx6ull-dhcom-drc02.dts23 * The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins.
24 * Therefore the UART RTS/CTS must be output on other DHCOM pins, see uart1
H A Dimx6ul-ccimx6ulsbcpro.dts62 /* CAN2 is multiplexed with UART2 RTS/CTS */
200 /* UART2 RTS/CTS muxed with CAN2 */
208 /* UART3 RTS/CTS muxed with CAN 1 */
/linux-6.15/arch/arm/boot/dts/ti/omap/
H A Dam335x-netcom-plus-2xx.dts26 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0) /* RTS */
39 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* RTS */
/linux-6.15/drivers/net/hamradio/
H A Dscc.c524 if((scc->wreg[5] & RTS) && scc->kiss.fulldup == KISS_DUPLEX_HALF) in scc_rxint()
938 scc->wreg[R5] |= RTS; in scc_key_trx()
940 or(scc,R5,RTS|TxENAB); /* set the RTS line and enable TX */ in scc_key_trx()
943 cl(scc,R5,RTS|TxENAB); in scc_key_trx()
972 scc->wreg[R5] |= RTS; in scc_key_trx()
974 or(scc,R5,RTS|TxENAB); /* enable tx */ in scc_key_trx()
977 cl(scc,R5,RTS|TxENAB); /* disable tx */ in scc_key_trx()
1110 if ( (grp1 & TXGROUP) && (scc2->wreg[R5] & RTS) ) in is_grouped()
1155 if ( !(scc->wreg[R5] & RTS) ) in t_dwait()
1346 if ( !(scc->wreg[R5] & RTS) ) in scc_set_param()
[all …]
H A Dz8530.h90 #define RTS 0x2 /* RTS */ macro
/linux-6.15/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64-orangepi-win.dts382 /* On Pi-2 connector, RTS/CTS optional */
389 /* On Pi-2 connector, RTS/CTS optional */
396 /* On Pi-2 connector (labeled for SPI1), RTS/CTS optional */
H A Dsun50i-a64-pine64.dts285 /* On Wifi/BT connector, with RTS/CTS */
306 /* On Euler connector, RTS/CTS optional */
/linux-6.15/arch/arm/boot/dts/st/
H A Dste-dbx5x0-pinctrl.dtsi21 pins = "GPIO1_AJ3", "GPIO3_AH3"; /* RTS+TXD */
32 pins = "GPIO1_AJ3"; /* RTS */
79 pins = "GPIO7_AG5"; /* RTS */
90 pins = "GPIO7_AG5"; /* RTS */
H A Dstm32mp157a-iot-box.dts57 /* Note: HW flow control is broken, hence using custom CTS/RTS gpios */
/linux-6.15/Documentation/devicetree/bindings/soc/fsl/cpm_qe/
H A Dserial.txt14 CTS, RTS, DCD, DSR, DTR, and RI.
/linux-6.15/arch/arm64/boot/dts/renesas/
H A Dr9a08g045s33-smarc-pmod1-type-3a.dtso37 <RZG2L_PORT_PINMUX(16, 1, 1)>; /* RTS# */
/linux-6.15/drivers/tty/serial/
H A Dzs.h143 #define RTS 0x2 /* RTS */ macro
H A Dip22zilog.h125 #define RTS 0x2 /* RTS */ macro
/linux-6.15/Documentation/hwmon/
H A Dsbtsi_temp.rst38 and physical interface of a typical 8-pin remote temperature sensor (RTS) on
/linux-6.15/Documentation/devicetree/bindings/gnss/
H A Dbrcm,bcm4751.yaml15 bus requires CTS/RTS support. The number of the capsule is more

1234