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Searched refs:RREG32_PCIE (Results 1 – 25 of 41) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dnbio_v6_1.c168 def = data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v6_1_update_medium_grain_clock_gating()
196 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v6_1_update_medium_grain_light_sleep()
217 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v6_1_get_clockgating_state()
222 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v6_1_get_clockgating_state()
273 def = data = RREG32_PCIE(smnPCIE_CI_CNTL); in nbio_v6_1_init_registers()
309 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v6_1_program_aspm()
316 def = data = RREG32_PCIE(smnPCIE_LC_CNTL7); in nbio_v6_1_program_aspm()
326 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); in nbio_v6_1_program_aspm()
356 def = data = RREG32_PCIE(smnPCIE_LC_CNTL6); in nbio_v6_1_program_aspm()
378 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v6_1_program_aspm()
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H A Dnbio_v2_3.c236 def = data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v2_3_update_medium_grain_clock_gating()
265 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v2_3_update_medium_grain_light_sleep()
286 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v2_3_get_clockgating_state()
291 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v2_3_get_clockgating_state()
352 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v2_3_enable_aspm()
408 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v2_3_program_aspm()
415 def = data = RREG32_PCIE(smnPCIE_LC_CNTL7); in nbio_v2_3_program_aspm()
425 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); in nbio_v2_3_program_aspm()
455 def = data = RREG32_PCIE(smnPCIE_LC_CNTL6); in nbio_v2_3_program_aspm()
477 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v2_3_program_aspm()
[all …]
H A Dnbio_v7_4.c259 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_4_update_medium_grain_light_sleep()
280 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v7_4_get_clockgating_state()
285 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_4_get_clockgating_state()
682 def = data = RREG32_PCIE(smnRCC_BIF_STRAP2); in nbio_v7_4_program_ltr()
707 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v7_4_program_aspm()
714 def = data = RREG32_PCIE(smnPCIE_LC_CNTL7); in nbio_v7_4_program_aspm()
724 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3); in nbio_v7_4_program_aspm()
729 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); in nbio_v7_4_program_aspm()
754 def = data = RREG32_PCIE(smnPCIE_LC_CNTL6); in nbio_v7_4_program_aspm()
776 def = data = RREG32_PCIE(smnPCIE_LC_CNTL); in nbio_v7_4_program_aspm()
[all …]
H A Dumc_v6_1.c50 rsmu_umc_val = RREG32_PCIE(rsmu_umc_addr * 4); in umc_v6_1_enable_umc_index_mode()
65 rsmu_umc_val = RREG32_PCIE(rsmu_umc_addr * 4); in umc_v6_1_disable_umc_index_mode()
80 rsmu_umc_val = RREG32_PCIE(rsmu_umc_addr * 4); in umc_v6_1_get_umc_index_mode_state()
119 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_1_clear_error_count_per_channel()
132 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_1_clear_error_count_per_channel()
197 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v6_1_query_correctable_error_count()
202 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_1_query_correctable_error_count()
212 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_1_query_correctable_error_count()
412 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v6_1_err_cnt_init_per_channel()
H A Dcik.c1580 tmp = RREG32_PCIE(ixPCIE_LC_STATUS1); in cik_pcie_gen3_enable()
1620 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()
1624 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()
1654 tmp = RREG32_PCIE(ixPCIE_LC_CNTL4); in cik_pcie_gen3_enable()
1713 orig = data = RREG32_PCIE(ixPCIE_P_CNTL); in cik_program_aspm()
1718 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); in cik_program_aspm()
1829 orig = data = RREG32_PCIE(ixPCIE_CNTL2); in cik_program_aspm()
1837 data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); in cik_program_aspm()
1840 data = RREG32_PCIE(ixPCIE_LC_STATUS1); in cik_program_aspm()
1922 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); in cik_get_pcie_usage()
[all …]
H A Dvi.c1110 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); in vi_enable_aspm()
1133 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL); in vi_program_aspm()
1147 orig = data = RREG32_PCIE(ixPCIE_LC_CNTL3); in vi_program_aspm()
1152 orig = data = RREG32_PCIE(ixPCIE_P_CNTL); in vi_program_aspm()
1219 orig = data = RREG32_PCIE(ixCPM_CONTROL); in vi_program_aspm()
1258 data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); in vi_program_aspm()
1259 data1 = RREG32_PCIE(ixPCIE_LC_STATUS1); in vi_program_aspm()
1390 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); in vi_get_pcie_usage()
1404 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK); in vi_get_pcie_replay_count()
1749 temp = data = RREG32_PCIE(ixPCIE_CNTL2); in vi_update_bif_medium_grain_light_sleep()
[all …]
H A Dumc_v8_14.c71 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v8_14_query_correctable_error_count()
86 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v8_14_query_uncorrectable_error_count()
133 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_14_err_cnt_init_per_channel()
H A Dumc_v8_7.c192 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v8_7_clear_error_count_per_channel()
205 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v8_7_clear_error_count_per_channel()
252 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_7_query_correctable_error_count()
257 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v8_7_query_correctable_error_count()
267 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v8_7_query_correctable_error_count()
402 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_7_err_cnt_init_per_channel()
H A Dumc_v6_7.c281 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count()
286 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count()
296 ecc_err_cnt = RREG32_PCIE((ecc_err_cnt_addr + umc_reg_offset) * 4); in umc_v6_7_query_correctable_error_count()
378 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_7_reset_error_count_per_channel()
391 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + in umc_v6_7_reset_error_count_per_channel()
499 ecc_ctrl = RREG32_PCIE((ecc_ctrl_addr + in umc_v6_7_query_ras_poison_mode_per_channel()
H A Dnbio_v7_0.c153 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK); in nbio_v7_0_update_medium_grain_clock_gating()
191 def = data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_0_update_medium_grain_light_sleep()
212 data = RREG32_PCIE(smnCPM_CONTROL); in nbio_v7_0_get_clockgating_state()
217 data = RREG32_PCIE(smnPCIE_CNTL2); in nbio_v7_0_get_clockgating_state()
H A Damdgpu_xgmi.c1386 data = RREG32_PCIE(xgmi_pcs_err_status_reg_arct[i]); in amdgpu_xgmi_legacy_query_ras_error_count()
1393 data = RREG32_PCIE(wafl_pcs_err_status_reg_arct[i]); in amdgpu_xgmi_legacy_query_ras_error_count()
1402 data = RREG32_PCIE(xgmi_pcs_err_status_reg_vg20[i]); in amdgpu_xgmi_legacy_query_ras_error_count()
1409 data = RREG32_PCIE(wafl_pcs_err_status_reg_vg20[i]); in amdgpu_xgmi_legacy_query_ras_error_count()
1418 data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_aldebaran[i]); in amdgpu_xgmi_legacy_query_ras_error_count()
1420 RREG32_PCIE(xgmi3x16_pcs_err_noncorrectable_mask_reg_aldebaran[i]); in amdgpu_xgmi_legacy_query_ras_error_count()
1427 data = RREG32_PCIE(walf_pcs_err_status_reg_aldebaran[i]); in amdgpu_xgmi_legacy_query_ras_error_count()
1429 RREG32_PCIE(walf_pcs_err_noncorrectable_mask_reg_aldebaran[i]); in amdgpu_xgmi_legacy_query_ras_error_count()
1445 data = RREG32_PCIE(xgmi3x16_pcs_err_status_reg_v6_4[i]); in amdgpu_xgmi_legacy_query_ras_error_count()
1447 RREG32_PCIE(xgmi3x16_pcs_err_noncorrectable_mask_reg_v6_4[i]); in amdgpu_xgmi_legacy_query_ras_error_count()
H A Dsoc15.c790 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK); in soc15_get_pcie_usage()
795 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); in soc15_get_pcie_usage()
796 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); in soc15_get_pcie_usage()
839 tmp = RREG32_PCIE(smnPCIE_PERF_CNTL_TXCLK3); in vega20_get_pcie_usage()
844 *count0 = RREG32_PCIE(smnPCIE_PERF_COUNT0_TXCLK3) | (cnt0_of << 32); in vega20_get_pcie_usage()
845 *count1 = RREG32_PCIE(smnPCIE_PERF_COUNT1_TXCLK3) | (cnt1_of << 32); in vega20_get_pcie_usage()
884 nak_r = RREG32_PCIE(smnPCIE_RX_NUM_NAK); in soc15_get_pcie_replay_count()
885 nak_g = RREG32_PCIE(smnPCIE_RX_NUM_NAK_GENERATED); in soc15_get_pcie_replay_count()
H A Dsi.c1617 tmp = RREG32_PCIE(ixPCIE_PERF_CNTL_TXCLK); in si_get_pcie_usage()
1622 *count0 = RREG32_PCIE(ixPCIE_PERF_COUNT0_TXCLK) | (cnt0_of << 32); in si_get_pcie_usage()
1623 *count1 = RREG32_PCIE(ixPCIE_PERF_COUNT1_TXCLK) | (cnt1_of << 32); in si_get_pcie_usage()
1631 nak_r = RREG32_PCIE(ixPCIE_RX_NUM_NAK); in si_get_pcie_replay_count()
1632 nak_g = RREG32_PCIE(ixPCIE_RX_NUM_NAK_GENERATED); in si_get_pcie_replay_count()
2271 tmp = RREG32_PCIE(PCIE_LC_STATUS1); in si_pcie_gen3_enable()
2432 orig = data = RREG32_PCIE(PCIE_P_CNTL); in si_program_aspm()
2595 orig = data = RREG32_PCIE(PCIE_CNTL2); in si_program_aspm()
2603 data = RREG32_PCIE(PCIE_LC_STATUS1); in si_program_aspm()
H A Dpsp_v3_1.c302 reg = RREG32_PCIE(smnMP1_FIRMWARE_FLAGS | 0x03b00000); in psp_v3_1_smu_reload_quirk()
H A Dumc_v8_10.c308 ecc_err_cnt_sel = RREG32_PCIE((ecc_err_cnt_sel_addr + umc_reg_offset) * 4); in umc_v8_10_err_cnt_init_per_channel()
H A Damdgpu_cgs.c64 return RREG32_PCIE(index); in amdgpu_cgs_read_ind_register()
H A Dnbio_v7_9.c474 val = RREG32_PCIE(smnPCIEP_NAK_COUNTER); in nbio_v7_9_get_pcie_replay_count()
/linux-6.15/drivers/gpu/drm/radeon/
H A Dr300.c94 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()
96 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_tlb_flush()
179 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_enable()
199 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_pcie_gart_disable()
597 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL); in rv370_debugfs_pcie_gart_info_show()
599 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE); in rv370_debugfs_pcie_gart_info_show()
601 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO); in rv370_debugfs_pcie_gart_info_show()
603 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI); in rv370_debugfs_pcie_gart_info_show()
605 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO); in rv370_debugfs_pcie_gart_info_show()
607 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI); in rv370_debugfs_pcie_gart_info_show()
[all …]
/linux-6.15/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu9_smumgr.c44 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu9_is_smc_ram_running()
H A Dvega20_smumgr.c54 mp1_fw_flags = RREG32_PCIE(MP1_Public | in vega20_is_smc_ram_running()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0.c165 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v13_0_load_microcode()
239 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v13_0_check_fw_status()
243 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v13_0_check_fw_status()
2068 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in smu_v13_0_get_current_pcie_link_width_level()
2088 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & in smu_v13_0_get_current_pcie_link_speed_level()
2545 ret = RREG32_PCIE(MP1_Public | in smu_v13_0_disable_pmfw_state()
H A Dsmu_v13_0_6_ppt.c1035 RREG32_PCIE(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff)); in smu_v13_0_6_check_fw_status()
2462 return REG_GET_FIELD(RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL), in smu_v13_0_6_get_current_pcie_link_width_level()
2473 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL); in smu_v13_0_6_get_current_pcie_link_speed()
2477 speed_level = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & in smu_v13_0_6_get_current_pcie_link_speed()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu12/
H A Dsmu_v12_0.c63 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v12_0_check_fw_status()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0.c141 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v14_0_load_microcode()
144 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v14_0_load_microcode()
214 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v14_0_check_fw_status()
217 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v14_0_check_fw_status()
/linux-6.15/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c166 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v11_0_load_microcode()
185 mp1_fw_flags = RREG32_PCIE(MP1_Public | in smu_v11_0_check_fw_status()
2105 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) & in smu_v11_0_get_current_pcie_link_width_level()
2125 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) & in smu_v11_0_get_current_pcie_link_speed_level()

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