1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd.
4 * Copyright (c) 2024 Collabora Ltd.
5 *
6 * Author: Algea Cao <[email protected]>
7 * Author: Cristian Ciocaltea <[email protected]>
8 */
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/delay.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_platform.h>
17 #include <linux/phy/phy.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/rational.h>
21 #include <linux/regmap.h>
22 #include <linux/reset.h>
23
24 #define GRF_HDPTX_CON0 0x00
25 #define HDPTX_I_PLL_EN BIT(7)
26 #define HDPTX_I_BIAS_EN BIT(6)
27 #define HDPTX_I_BGR_EN BIT(5)
28 #define HDPTX_MODE_SEL BIT(0)
29 #define GRF_HDPTX_STATUS 0x80
30 #define HDPTX_O_PLL_LOCK_DONE BIT(3)
31 #define HDPTX_O_PHY_CLK_RDY BIT(2)
32 #define HDPTX_O_PHY_RDY BIT(1)
33 #define HDPTX_O_SB_RDY BIT(0)
34
35 #define HDTPX_REG(_n, _min, _max) \
36 ( \
37 BUILD_BUG_ON_ZERO((0x##_n) < (0x##_min)) + \
38 BUILD_BUG_ON_ZERO((0x##_n) > (0x##_max)) + \
39 ((0x##_n) * 4) \
40 )
41
42 #define CMN_REG(n) HDTPX_REG(n, 0000, 00a7)
43 #define SB_REG(n) HDTPX_REG(n, 0100, 0129)
44 #define LNTOP_REG(n) HDTPX_REG(n, 0200, 0229)
45 #define LANE_REG(n) HDTPX_REG(n, 0300, 062d)
46
47 /* CMN_REG(0008) */
48 #define OVRD_LCPLL_EN_MASK BIT(7)
49 #define LCPLL_EN_MASK BIT(6)
50 #define LCPLL_LCVCO_MODE_EN_MASK BIT(4)
51 /* CMN_REG(001e) */
52 #define LCPLL_PI_EN_MASK BIT(5)
53 #define LCPLL_100M_CLK_EN_MASK BIT(0)
54 /* CMN_REG(0025) */
55 #define LCPLL_PMS_IQDIV_RSTN_MASK BIT(4)
56 /* CMN_REG(0028) */
57 #define LCPLL_SDC_FRAC_EN_MASK BIT(2)
58 #define LCPLL_SDC_FRAC_RSTN_MASK BIT(0)
59 /* CMN_REG(002d) */
60 #define LCPLL_SDC_N_MASK GENMASK(3, 1)
61 /* CMN_REG(002e) */
62 #define LCPLL_SDC_NUMBERATOR_MASK GENMASK(5, 0)
63 /* CMN_REG(002f) */
64 #define LCPLL_SDC_DENOMINATOR_MASK GENMASK(7, 2)
65 #define LCPLL_SDC_NDIV_RSTN_MASK BIT(0)
66 /* CMN_REG(003c) */
67 #define ANA_LCPLL_RESERVED7_MASK BIT(7)
68 /* CMN_REG(003d) */
69 #define OVRD_ROPLL_EN_MASK BIT(7)
70 #define ROPLL_EN_MASK BIT(6)
71 #define ROPLL_LCVCO_EN_MASK BIT(4)
72 /* CMN_REG(0046) */
73 #define ROPLL_ANA_CPP_CTRL_COARSE_MASK GENMASK(7, 4)
74 #define ROPLL_ANA_CPP_CTRL_FINE_MASK GENMASK(3, 0)
75 /* CMN_REG(0047) */
76 #define ROPLL_ANA_LPF_C_SEL_COARSE_MASK GENMASK(5, 3)
77 #define ROPLL_ANA_LPF_C_SEL_FINE_MASK GENMASK(2, 0)
78 /* CMN_REG(004e) */
79 #define ROPLL_PI_EN_MASK BIT(5)
80 /* CMN_REG(0051) */
81 #define ROPLL_PMS_MDIV_MASK GENMASK(7, 0)
82 /* CMN_REG(0055) */
83 #define ROPLL_PMS_MDIV_AFC_MASK GENMASK(7, 0)
84 /* CMN_REG(0059) */
85 #define ANA_ROPLL_PMS_PDIV_MASK GENMASK(7, 4)
86 #define ANA_ROPLL_PMS_REFDIV_MASK GENMASK(3, 0)
87 /* CMN_REG(005a) */
88 #define ROPLL_PMS_SDIV_RBR_MASK GENMASK(7, 4)
89 #define ROPLL_PMS_SDIV_HBR_MASK GENMASK(3, 0)
90 /* CMN_REG(005b) */
91 #define ROPLL_PMS_SDIV_HBR2_MASK GENMASK(7, 4)
92 /* CMN_REG(005c) */
93 #define ROPLL_PMS_IQDIV_RSTN_MASK BIT(5)
94 /* CMN_REG(005e) */
95 #define ROPLL_SDM_EN_MASK BIT(6)
96 #define OVRD_ROPLL_SDM_RSTN_MASK BIT(5)
97 #define ROPLL_SDM_RSTN_MASK BIT(4)
98 #define ROPLL_SDC_FRAC_EN_RBR_MASK BIT(3)
99 #define ROPLL_SDC_FRAC_EN_HBR_MASK BIT(2)
100 #define ROPLL_SDC_FRAC_EN_HBR2_MASK BIT(1)
101 #define ROPLL_SDM_FRAC_EN_HBR3_MASK BIT(0)
102 /* CMN_REG(005f) */
103 #define OVRD_ROPLL_SDC_RSTN_MASK BIT(5)
104 #define ROPLL_SDC_RSTN_MASK BIT(4)
105 /* CMN_REG(0060) */
106 #define ROPLL_SDM_DENOMINATOR_MASK GENMASK(7, 0)
107 /* CMN_REG(0064) */
108 #define ROPLL_SDM_NUM_SIGN_RBR_MASK BIT(3)
109 #define ROPLL_SDM_NUM_SIGN_HBR_MASK BIT(2)
110 #define ROPLL_SDM_NUM_SIGN_HBR2_MASK BIT(1)
111 /* CMN_REG(0065) */
112 #define ROPLL_SDM_NUM_MASK GENMASK(7, 0)
113 /* CMN_REG(0069) */
114 #define ROPLL_SDC_N_RBR_MASK GENMASK(2, 0)
115 /* CMN_REG(006a) */
116 #define ROPLL_SDC_N_HBR_MASK GENMASK(5, 3)
117 #define ROPLL_SDC_N_HBR2_MASK GENMASK(2, 0)
118 /* CMN_REG(006b) */
119 #define ROPLL_SDC_N_HBR3_MASK GENMASK(3, 1)
120 /* CMN_REG(006c) */
121 #define ROPLL_SDC_NUM_MASK GENMASK(5, 0)
122 /* cmn_reg0070 */
123 #define ROPLL_SDC_DENO_MASK GENMASK(5, 0)
124 /* CMN_REG(0074) */
125 #define OVRD_ROPLL_SDC_NDIV_RSTN_MASK BIT(3)
126 #define ROPLL_SDC_NDIV_RSTN_MASK BIT(2)
127 #define OVRD_ROPLL_SSC_EN_MASK BIT(1)
128 #define ROPLL_SSC_EN_MASK BIT(0)
129 /* CMN_REG(0075) */
130 #define ANA_ROPLL_SSC_FM_DEVIATION_MASK GENMASK(5, 0)
131 /* CMN_REG(0076) */
132 #define ANA_ROPLL_SSC_FM_FREQ_MASK GENMASK(6, 2)
133 /* CMN_REG(0077) */
134 #define ANA_ROPLL_SSC_CLK_DIV_SEL_MASK GENMASK(6, 3)
135 /* CMN_REG(0081) */
136 #define OVRD_PLL_CD_CLK_EN_MASK BIT(8)
137 #define ANA_PLL_CD_TX_SER_RATE_SEL_MASK BIT(3)
138 #define ANA_PLL_CD_HSCLK_WEST_EN_MASK BIT(1)
139 #define ANA_PLL_CD_HSCLK_EAST_EN_MASK BIT(0)
140 /* CMN_REG(0082) */
141 #define ANA_PLL_CD_VREG_GAIN_CTRL_MASK GENMASK(3, 0)
142 /* CMN_REG(0083) */
143 #define ANA_PLL_CD_VREG_ICTRL_MASK GENMASK(6, 5)
144 /* CMN_REG(0084) */
145 #define PLL_LCRO_CLK_SEL_MASK BIT(5)
146 /* CMN_REG(0085) */
147 #define ANA_PLL_SYNC_LOSS_DET_MODE_MASK GENMASK(1, 0)
148 /* CMN_REG(0086) */
149 #define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4)
150 #define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1)
151 #define PLL_PCG_CLK_EN_MASK BIT(0)
152 /* CMN_REG(0087) */
153 #define ANA_PLL_FRL_MODE_EN_MASK BIT(3)
154 #define ANA_PLL_TX_HS_CLK_EN_MASK BIT(2)
155 /* CMN_REG(0089) */
156 #define LCPLL_ALONE_MODE_MASK BIT(1)
157 /* CMN_REG(0095) */
158 #define DP_TX_LINK_BW_MASK GENMASK(1, 0)
159 /* CMN_REG(0097) */
160 #define DIG_CLK_SEL_MASK BIT(1)
161 #define LCPLL_REF BIT(1)
162 #define ROPLL_REF 0
163 /* CMN_REG(0099) */
164 #define SSC_EN_MASK GENMASK(7, 6)
165 #define CMN_ROPLL_ALONE_MODE_MASK BIT(2)
166 #define ROPLL_ALONE_MODE BIT(2)
167 /* CMN_REG(009a) */
168 #define HS_SPEED_SEL_MASK BIT(0)
169 #define DIV_10_CLOCK BIT(0)
170 /* CMN_REG(009b) */
171 #define LS_SPEED_SEL_MASK BIT(4)
172 #define LINK_SYMBOL_CLOCK BIT(4)
173 #define LINK_SYMBOL_CLOCK1_2 0
174
175 /* SB_REG(0102) */
176 #define OVRD_SB_RXTERM_EN_MASK BIT(5)
177 #define SB_RXTERM_EN_MASK BIT(4)
178 #define ANA_SB_RXTERM_OFFSP_MASK GENMASK(3, 0)
179 /* SB_REG(0103) */
180 #define ANA_SB_RXTERM_OFFSN_MASK GENMASK(6, 3)
181 #define OVRD_SB_RX_RESCAL_DONE_MASK BIT(1)
182 #define SB_RX_RESCAL_DONE_MASK BIT(0)
183 /* SB_REG(0104) */
184 #define OVRD_SB_EN_MASK BIT(5)
185 #define SB_EN_MASK BIT(4)
186 #define OVRD_SB_AUX_EN_MASK BIT(1)
187 #define SB_AUX_EN_MASK BIT(0)
188 /* SB_REG(0105) */
189 #define OVRD_SB_EARC_CMDC_EN_MASK BIT(6)
190 #define SB_EARC_CMDC_EN_MASK BIT(5)
191 #define ANA_SB_TX_HLVL_PROG_MASK GENMASK(2, 0)
192 /* SB_REG(0106) */
193 #define ANA_SB_TX_LLVL_PROG_MASK GENMASK(6, 4)
194 /* SB_REG(0109) */
195 #define ANA_SB_DMRX_AFC_DIV_RATIO_MASK GENMASK(2, 0)
196 /* SB_REG(010d) */
197 #define ANA_SB_DMRX_LPBK_DATA_MASK BIT(4)
198 /* SB_REG(010f) */
199 #define OVRD_SB_VREG_EN_MASK BIT(7)
200 #define SB_VREG_EN_MASK BIT(6)
201 #define OVRD_SB_VREG_LPF_BYPASS_MASK BIT(5)
202 #define SB_VREG_LPF_BYPASS_MASK BIT(4)
203 #define ANA_SB_VREG_GAIN_CTRL_MASK GENMASK(3, 0)
204 /* SB_REG(0110) */
205 #define ANA_SB_VREG_OUT_SEL_MASK BIT(1)
206 #define ANA_SB_VREG_REF_SEL_MASK BIT(0)
207 /* SB_REG(0113) */
208 #define SB_RX_RCAL_OPT_CODE_MASK GENMASK(5, 4)
209 #define SB_RX_RTERM_CTRL_MASK GENMASK(3, 0)
210 /* SB_REG(0114) */
211 #define SB_TG_SB_EN_DELAY_TIME_MASK GENMASK(5, 3)
212 #define SB_TG_RXTERM_EN_DELAY_TIME_MASK GENMASK(2, 0)
213 /* SB_REG(0115) */
214 #define SB_READY_DELAY_TIME_MASK GENMASK(5, 3)
215 #define SB_TG_OSC_EN_DELAY_TIME_MASK GENMASK(2, 0)
216 /* SB_REG(0116) */
217 #define AFC_RSTN_DELAY_TIME_MASK GENMASK(6, 4)
218 /* SB_REG(0117) */
219 #define FAST_PULSE_TIME_MASK GENMASK(3, 0)
220 /* SB_REG(0118) */
221 #define SB_TG_EARC_DMRX_RECVRD_CLK_CNT_MASK GENMASK(7, 0)
222 /* SB_REG(011a) */
223 #define SB_TG_CNT_RUN_NO_7_0_MASK GENMASK(7, 0)
224 /* SB_REG(011b) */
225 #define SB_EARC_SIG_DET_BYPASS_MASK BIT(4)
226 #define SB_AFC_TOL_MASK GENMASK(3, 0)
227 /* SB_REG(011c) */
228 #define SB_AFC_STB_NUM_MASK GENMASK(3, 0)
229 /* SB_REG(011d) */
230 #define SB_TG_OSC_CNT_MIN_MASK GENMASK(7, 0)
231 /* SB_REG(011e) */
232 #define SB_TG_OSC_CNT_MAX_MASK GENMASK(7, 0)
233 /* SB_REG(011f) */
234 #define SB_PWM_AFC_CTRL_MASK GENMASK(7, 2)
235 #define SB_RCAL_RSTN_MASK BIT(1)
236 /* SB_REG(0120) */
237 #define SB_AUX_EN_IN_MASK BIT(7)
238 #define SB_EARC_EN_MASK BIT(1)
239 #define SB_EARC_AFC_EN_MASK BIT(2)
240 /* SB_REG(0123) */
241 #define OVRD_SB_READY_MASK BIT(5)
242 #define SB_READY_MASK BIT(4)
243
244 /* LNTOP_REG(0200) */
245 #define PROTOCOL_SEL_MASK BIT(2)
246 #define HDMI_MODE BIT(2)
247 #define HDMI_TMDS_FRL_SEL BIT(1)
248 /* LNTOP_REG(0206) */
249 #define DATA_BUS_WIDTH_MASK GENMASK(2, 1)
250 #define DATA_BUS_WIDTH_SEL_MASK BIT(0)
251 #define DATA_BUS_36_40 BIT(0)
252 /* LNTOP_REG(0207) */
253 #define LANE_EN_MASK 0xf
254 #define ALL_LANE_EN 0xf
255
256 /* LANE_REG(0301) */
257 #define OVRD_LN_TX_DRV_EI_EN_MASK BIT(7)
258 #define LN_TX_DRV_EI_EN_MASK BIT(6)
259 /* LANE_REG(0303) */
260 #define OVRD_LN_TX_DRV_LVL_CTRL_MASK BIT(5)
261 #define LN_TX_DRV_LVL_CTRL_MASK GENMASK(4, 0)
262 /* LANE_REG(0304) */
263 #define OVRD_LN_TX_DRV_POST_LVL_CTRL_MASK BIT(4)
264 #define LN_TX_DRV_POST_LVL_CTRL_MASK GENMASK(3, 0)
265 /* LANE_REG(0305) */
266 #define OVRD_LN_TX_DRV_PRE_LVL_CTRL_MASK BIT(6)
267 #define LN_TX_DRV_PRE_LVL_CTRL_MASK GENMASK(5, 2)
268 /* LANE_REG(0306) */
269 #define LN_ANA_TX_DRV_IDRV_IDN_CTRL_MASK GENMASK(7, 5)
270 #define LN_ANA_TX_DRV_IDRV_IUP_CTRL_MASK GENMASK(4, 2)
271 #define LN_ANA_TX_DRV_ACCDRV_EN_MASK BIT(0)
272 /* LANE_REG(0307) */
273 #define LN_ANA_TX_DRV_ACCDRV_POL_SEL_MASK BIT(6)
274 #define LN_ANA_TX_DRV_ACCDRV_CTRL_MASK GENMASK(5, 3)
275 /* LANE_REG(030a) */
276 #define LN_ANA_TX_JEQ_EN_MASK BIT(4)
277 #define LN_TX_JEQ_EVEN_CTRL_RBR_MASK GENMASK(3, 0)
278 /* LANE_REG(030b) */
279 #define LN_TX_JEQ_EVEN_CTRL_HBR_MASK GENMASK(7, 4)
280 #define LN_TX_JEQ_EVEN_CTRL_HBR2_MASK GENMASK(3, 0)
281 /* LANE_REG(030c) */
282 #define LN_TX_JEQ_ODD_CTRL_RBR_MASK GENMASK(3, 0)
283 /* LANE_REG(030d) */
284 #define LN_TX_JEQ_ODD_CTRL_HBR_MASK GENMASK(7, 4)
285 #define LN_TX_JEQ_ODD_CTRL_HBR2_MASK GENMASK(3, 0)
286 /* LANE_REG(0310) */
287 #define LN_ANA_TX_SYNC_LOSS_DET_MODE_MASK GENMASK(1, 0)
288 /* LANE_REG(0311) */
289 #define LN_TX_SER_40BIT_EN_RBR_MASK BIT(3)
290 #define LN_TX_SER_40BIT_EN_HBR_MASK BIT(2)
291 #define LN_TX_SER_40BIT_EN_HBR2_MASK BIT(1)
292 /* LANE_REG(0312) */
293 #define LN0_TX_SER_RATE_SEL_RBR_MASK BIT(5)
294 #define LN0_TX_SER_RATE_SEL_HBR_MASK BIT(4)
295 #define LN0_TX_SER_RATE_SEL_HBR2_MASK BIT(3)
296 #define LN0_TX_SER_RATE_SEL_HBR3_MASK BIT(2)
297 /* LANE_REG(0316) */
298 #define LN_ANA_TX_SER_VREG_GAIN_CTRL_MASK GENMASK(3, 0)
299 /* LANE_REG(031B) */
300 #define LN_ANA_TX_RESERVED_MASK GENMASK(7, 0)
301 /* LANE_REG(031e) */
302 #define LN_POLARITY_INV_MASK BIT(2)
303 #define LN_LANE_MODE_MASK BIT(1)
304
305 /* LANE_REG(0412) */
306 #define LN1_TX_SER_RATE_SEL_RBR_MASK BIT(5)
307 #define LN1_TX_SER_RATE_SEL_HBR_MASK BIT(4)
308 #define LN1_TX_SER_RATE_SEL_HBR2_MASK BIT(3)
309 #define LN1_TX_SER_RATE_SEL_HBR3_MASK BIT(2)
310
311 /* LANE_REG(0512) */
312 #define LN2_TX_SER_RATE_SEL_RBR_MASK BIT(5)
313 #define LN2_TX_SER_RATE_SEL_HBR_MASK BIT(4)
314 #define LN2_TX_SER_RATE_SEL_HBR2_MASK BIT(3)
315 #define LN2_TX_SER_RATE_SEL_HBR3_MASK BIT(2)
316
317 /* LANE_REG(0612) */
318 #define LN3_TX_SER_RATE_SEL_RBR_MASK BIT(5)
319 #define LN3_TX_SER_RATE_SEL_HBR_MASK BIT(4)
320 #define LN3_TX_SER_RATE_SEL_HBR2_MASK BIT(3)
321 #define LN3_TX_SER_RATE_SEL_HBR3_MASK BIT(2)
322
323 #define HDMI20_MAX_RATE 600000000
324
325 enum dp_link_rate {
326 DP_BW_RBR,
327 DP_BW_HBR,
328 DP_BW_HBR2,
329 };
330
331 struct lcpll_config {
332 u32 bit_rate;
333 u8 lcvco_mode_en;
334 u8 pi_en;
335 u8 clk_en_100m;
336 u8 pms_mdiv;
337 u8 pms_mdiv_afc;
338 u8 pms_pdiv;
339 u8 pms_refdiv;
340 u8 pms_sdiv;
341 u8 pi_cdiv_rstn;
342 u8 pi_cdiv_sel;
343 u8 sdm_en;
344 u8 sdm_rstn;
345 u8 sdc_frac_en;
346 u8 sdc_rstn;
347 u8 sdm_deno;
348 u8 sdm_num_sign;
349 u8 sdm_num;
350 u8 sdc_n;
351 u8 sdc_n2;
352 u8 sdc_num;
353 u8 sdc_deno;
354 u8 sdc_ndiv_rstn;
355 u8 ssc_en;
356 u8 ssc_fm_dev;
357 u8 ssc_fm_freq;
358 u8 ssc_clk_div_sel;
359 u8 cd_tx_ser_rate_sel;
360 };
361
362 struct ropll_config {
363 u32 bit_rate;
364 u8 pms_mdiv;
365 u8 pms_mdiv_afc;
366 u8 pms_pdiv;
367 u8 pms_refdiv;
368 u8 pms_sdiv;
369 u8 pms_iqdiv_rstn;
370 u8 ref_clk_sel;
371 u8 sdm_en;
372 u8 sdm_rstn;
373 u8 sdc_frac_en;
374 u8 sdc_rstn;
375 u8 sdm_clk_div;
376 u8 sdm_deno;
377 u8 sdm_num_sign;
378 u8 sdm_num;
379 u8 sdc_n;
380 u8 sdc_num;
381 u8 sdc_deno;
382 u8 sdc_ndiv_rstn;
383 u8 ssc_en;
384 u8 ssc_fm_dev;
385 u8 ssc_fm_freq;
386 u8 ssc_clk_div_sel;
387 u8 ana_cpp_ctrl;
388 u8 ana_lpf_c_sel;
389 u8 cd_tx_ser_rate_sel;
390 };
391
392 struct tx_drv_ctrl {
393 u8 tx_drv_lvl_ctrl;
394 u8 tx_drv_post_lvl_ctrl;
395 u8 ana_tx_drv_idrv_idn_ctrl;
396 u8 ana_tx_drv_idrv_iup_ctrl;
397 u8 ana_tx_drv_accdrv_en;
398 u8 ana_tx_drv_accdrv_ctrl;
399 u8 tx_drv_pre_lvl_ctrl;
400 u8 ana_tx_jeq_en;
401 u8 tx_jeq_even_ctrl;
402 u8 tx_jeq_odd_ctrl;
403 };
404
405 enum rk_hdptx_reset {
406 RST_APB = 0,
407 RST_INIT,
408 RST_CMN,
409 RST_LANE,
410 RST_MAX
411 };
412
413 #define MAX_HDPTX_PHY_NUM 2
414
415 struct rk_hdptx_phy_cfg {
416 unsigned int num_phys;
417 unsigned int phy_ids[MAX_HDPTX_PHY_NUM];
418 };
419
420 struct rk_hdptx_phy {
421 struct device *dev;
422 struct regmap *regmap;
423 struct regmap *grf;
424
425 /* PHY const config */
426 const struct rk_hdptx_phy_cfg *cfgs;
427 int phy_id;
428
429 struct phy *phy;
430 struct phy_config *phy_cfg;
431 struct clk_bulk_data *clks;
432 int nr_clks;
433 struct reset_control_bulk_data rsts[RST_MAX];
434
435 /* clk provider */
436 struct clk_hw hw;
437 unsigned long rate;
438
439 atomic_t usage_count;
440
441 /* used for dp mode */
442 unsigned int link_rate;
443 unsigned int lanes;
444 };
445
446 static const struct ropll_config ropll_tmds_cfg[] = {
447 { 5940000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
448 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
449 { 3712500, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
450 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
451 { 2970000, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
452 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
453 { 1620000, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10,
454 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
455 { 1856250, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
456 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
457 { 1540000, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1,
458 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
459 { 1485000, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5,
460 0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
461 { 1462500, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1,
462 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
463 { 1190000, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1,
464 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
465 { 1065000, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1,
466 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
467 { 1080000, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
468 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
469 { 855000, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1,
470 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
471 { 835000, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0,
472 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
473 { 928125, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
474 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
475 { 742500, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0,
476 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
477 { 650000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1,
478 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
479 { 502500, 84, 84, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 11, 1, 4, 5,
480 4, 11, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
481 { 337500, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5,
482 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
483 { 400000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
484 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
485 { 270000, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0,
486 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
487 { 251750, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1,
488 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, },
489 };
490
491 static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = {
492 REG_SEQ0(CMN_REG(0009), 0x0c),
493 REG_SEQ0(CMN_REG(000a), 0x83),
494 REG_SEQ0(CMN_REG(000b), 0x06),
495 REG_SEQ0(CMN_REG(000c), 0x20),
496 REG_SEQ0(CMN_REG(000d), 0xb8),
497 REG_SEQ0(CMN_REG(000e), 0x0f),
498 REG_SEQ0(CMN_REG(000f), 0x0f),
499 REG_SEQ0(CMN_REG(0010), 0x04),
500 REG_SEQ0(CMN_REG(0011), 0x00),
501 REG_SEQ0(CMN_REG(0012), 0x26),
502 REG_SEQ0(CMN_REG(0013), 0x22),
503 REG_SEQ0(CMN_REG(0014), 0x24),
504 REG_SEQ0(CMN_REG(0015), 0x77),
505 REG_SEQ0(CMN_REG(0016), 0x08),
506 REG_SEQ0(CMN_REG(0017), 0x00),
507 REG_SEQ0(CMN_REG(0018), 0x04),
508 REG_SEQ0(CMN_REG(0019), 0x48),
509 REG_SEQ0(CMN_REG(001a), 0x01),
510 REG_SEQ0(CMN_REG(001b), 0x00),
511 REG_SEQ0(CMN_REG(001c), 0x01),
512 REG_SEQ0(CMN_REG(001d), 0x64),
513 REG_SEQ0(CMN_REG(001f), 0x00),
514 REG_SEQ0(CMN_REG(0026), 0x53),
515 REG_SEQ0(CMN_REG(0029), 0x01),
516 REG_SEQ0(CMN_REG(0030), 0x00),
517 REG_SEQ0(CMN_REG(0031), 0x20),
518 REG_SEQ0(CMN_REG(0032), 0x30),
519 REG_SEQ0(CMN_REG(0033), 0x0b),
520 REG_SEQ0(CMN_REG(0034), 0x23),
521 REG_SEQ0(CMN_REG(0035), 0x00),
522 REG_SEQ0(CMN_REG(0038), 0x00),
523 REG_SEQ0(CMN_REG(0039), 0x00),
524 REG_SEQ0(CMN_REG(003a), 0x00),
525 REG_SEQ0(CMN_REG(003b), 0x00),
526 REG_SEQ0(CMN_REG(003c), 0x80),
527 REG_SEQ0(CMN_REG(003e), 0x0c),
528 REG_SEQ0(CMN_REG(003f), 0x83),
529 REG_SEQ0(CMN_REG(0040), 0x06),
530 REG_SEQ0(CMN_REG(0041), 0x20),
531 REG_SEQ0(CMN_REG(0042), 0xb8),
532 REG_SEQ0(CMN_REG(0043), 0x00),
533 REG_SEQ0(CMN_REG(0044), 0x46),
534 REG_SEQ0(CMN_REG(0045), 0x24),
535 REG_SEQ0(CMN_REG(0046), 0xff),
536 REG_SEQ0(CMN_REG(0047), 0x00),
537 REG_SEQ0(CMN_REG(0048), 0x44),
538 REG_SEQ0(CMN_REG(0049), 0xfa),
539 REG_SEQ0(CMN_REG(004a), 0x08),
540 REG_SEQ0(CMN_REG(004b), 0x00),
541 REG_SEQ0(CMN_REG(004c), 0x01),
542 REG_SEQ0(CMN_REG(004d), 0x64),
543 REG_SEQ0(CMN_REG(004e), 0x14),
544 REG_SEQ0(CMN_REG(004f), 0x00),
545 REG_SEQ0(CMN_REG(0050), 0x00),
546 REG_SEQ0(CMN_REG(005d), 0x0c),
547 REG_SEQ0(CMN_REG(005f), 0x01),
548 REG_SEQ0(CMN_REG(006b), 0x04),
549 REG_SEQ0(CMN_REG(0073), 0x30),
550 REG_SEQ0(CMN_REG(0074), 0x00),
551 REG_SEQ0(CMN_REG(0075), 0x20),
552 REG_SEQ0(CMN_REG(0076), 0x30),
553 REG_SEQ0(CMN_REG(0077), 0x08),
554 REG_SEQ0(CMN_REG(0078), 0x0c),
555 REG_SEQ0(CMN_REG(0079), 0x00),
556 REG_SEQ0(CMN_REG(007b), 0x00),
557 REG_SEQ0(CMN_REG(007c), 0x00),
558 REG_SEQ0(CMN_REG(007d), 0x00),
559 REG_SEQ0(CMN_REG(007e), 0x00),
560 REG_SEQ0(CMN_REG(007f), 0x00),
561 REG_SEQ0(CMN_REG(0080), 0x00),
562 REG_SEQ0(CMN_REG(0081), 0x09),
563 REG_SEQ0(CMN_REG(0082), 0x04),
564 REG_SEQ0(CMN_REG(0083), 0x24),
565 REG_SEQ0(CMN_REG(0084), 0x20),
566 REG_SEQ0(CMN_REG(0085), 0x03),
567 REG_SEQ0(CMN_REG(0086), 0x01),
568 REG_SEQ0(CMN_REG(0087), 0x0c),
569 REG_SEQ0(CMN_REG(008a), 0x55),
570 REG_SEQ0(CMN_REG(008b), 0x25),
571 REG_SEQ0(CMN_REG(008c), 0x2c),
572 REG_SEQ0(CMN_REG(008d), 0x22),
573 REG_SEQ0(CMN_REG(008e), 0x14),
574 REG_SEQ0(CMN_REG(008f), 0x20),
575 REG_SEQ0(CMN_REG(0090), 0x00),
576 REG_SEQ0(CMN_REG(0091), 0x00),
577 REG_SEQ0(CMN_REG(0092), 0x00),
578 REG_SEQ0(CMN_REG(0093), 0x00),
579 REG_SEQ0(CMN_REG(009a), 0x11),
580 REG_SEQ0(CMN_REG(009b), 0x10),
581 };
582
583 static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = {
584 REG_SEQ0(CMN_REG(0008), 0x00),
585 REG_SEQ0(CMN_REG(0011), 0x01),
586 REG_SEQ0(CMN_REG(0017), 0x20),
587 REG_SEQ0(CMN_REG(001e), 0x14),
588 REG_SEQ0(CMN_REG(0020), 0x00),
589 REG_SEQ0(CMN_REG(0021), 0x00),
590 REG_SEQ0(CMN_REG(0022), 0x11),
591 REG_SEQ0(CMN_REG(0023), 0x00),
592 REG_SEQ0(CMN_REG(0024), 0x00),
593 REG_SEQ0(CMN_REG(0025), 0x53),
594 REG_SEQ0(CMN_REG(0026), 0x00),
595 REG_SEQ0(CMN_REG(0027), 0x00),
596 REG_SEQ0(CMN_REG(0028), 0x01),
597 REG_SEQ0(CMN_REG(002a), 0x00),
598 REG_SEQ0(CMN_REG(002b), 0x00),
599 REG_SEQ0(CMN_REG(002c), 0x00),
600 REG_SEQ0(CMN_REG(002d), 0x00),
601 REG_SEQ0(CMN_REG(002e), 0x04),
602 REG_SEQ0(CMN_REG(002f), 0x00),
603 REG_SEQ0(CMN_REG(0030), 0x20),
604 REG_SEQ0(CMN_REG(0031), 0x30),
605 REG_SEQ0(CMN_REG(0032), 0x0b),
606 REG_SEQ0(CMN_REG(0033), 0x23),
607 REG_SEQ0(CMN_REG(0034), 0x00),
608 REG_SEQ0(CMN_REG(003d), 0x40),
609 REG_SEQ0(CMN_REG(0042), 0x78),
610 REG_SEQ0(CMN_REG(004e), 0x34),
611 REG_SEQ0(CMN_REG(005c), 0x25),
612 REG_SEQ0(CMN_REG(005e), 0x4f),
613 REG_SEQ0(CMN_REG(0074), 0x04),
614 REG_SEQ0(CMN_REG(0081), 0x01),
615 REG_SEQ0(CMN_REG(0087), 0x04),
616 REG_SEQ0(CMN_REG(0089), 0x00),
617 REG_SEQ0(CMN_REG(0095), 0x00),
618 REG_SEQ0(CMN_REG(0097), 0x02),
619 REG_SEQ0(CMN_REG(0099), 0x04),
620 REG_SEQ0(CMN_REG(009b), 0x00),
621 };
622
623 static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] = {
624 REG_SEQ0(SB_REG(0114), 0x00),
625 REG_SEQ0(SB_REG(0115), 0x00),
626 REG_SEQ0(SB_REG(0116), 0x00),
627 REG_SEQ0(SB_REG(0117), 0x00),
628 };
629
630 static const struct reg_sequence rk_hdtpx_tmds_lntop_highbr_seq[] = {
631 REG_SEQ0(LNTOP_REG(0201), 0x00),
632 REG_SEQ0(LNTOP_REG(0202), 0x00),
633 REG_SEQ0(LNTOP_REG(0203), 0x0f),
634 REG_SEQ0(LNTOP_REG(0204), 0xff),
635 REG_SEQ0(LNTOP_REG(0205), 0xff),
636 };
637
638 static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = {
639 REG_SEQ0(LNTOP_REG(0201), 0x07),
640 REG_SEQ0(LNTOP_REG(0202), 0xc1),
641 REG_SEQ0(LNTOP_REG(0203), 0xf0),
642 REG_SEQ0(LNTOP_REG(0204), 0x7c),
643 REG_SEQ0(LNTOP_REG(0205), 0x1f),
644 };
645
646 static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = {
647 REG_SEQ0(LANE_REG(0303), 0x0c),
648 REG_SEQ0(LANE_REG(0307), 0x20),
649 REG_SEQ0(LANE_REG(030a), 0x17),
650 REG_SEQ0(LANE_REG(030b), 0x77),
651 REG_SEQ0(LANE_REG(030c), 0x77),
652 REG_SEQ0(LANE_REG(030d), 0x77),
653 REG_SEQ0(LANE_REG(030e), 0x38),
654 REG_SEQ0(LANE_REG(0310), 0x03),
655 REG_SEQ0(LANE_REG(0311), 0x0f),
656 REG_SEQ0(LANE_REG(0316), 0x02),
657 REG_SEQ0(LANE_REG(031b), 0x01),
658 REG_SEQ0(LANE_REG(031f), 0x15),
659 REG_SEQ0(LANE_REG(0320), 0xa0),
660 REG_SEQ0(LANE_REG(0403), 0x0c),
661 REG_SEQ0(LANE_REG(0407), 0x20),
662 REG_SEQ0(LANE_REG(040a), 0x17),
663 REG_SEQ0(LANE_REG(040b), 0x77),
664 REG_SEQ0(LANE_REG(040c), 0x77),
665 REG_SEQ0(LANE_REG(040d), 0x77),
666 REG_SEQ0(LANE_REG(040e), 0x38),
667 REG_SEQ0(LANE_REG(0410), 0x03),
668 REG_SEQ0(LANE_REG(0411), 0x0f),
669 REG_SEQ0(LANE_REG(0416), 0x02),
670 REG_SEQ0(LANE_REG(041b), 0x01),
671 REG_SEQ0(LANE_REG(041f), 0x15),
672 REG_SEQ0(LANE_REG(0420), 0xa0),
673 REG_SEQ0(LANE_REG(0503), 0x0c),
674 REG_SEQ0(LANE_REG(0507), 0x20),
675 REG_SEQ0(LANE_REG(050a), 0x17),
676 REG_SEQ0(LANE_REG(050b), 0x77),
677 REG_SEQ0(LANE_REG(050c), 0x77),
678 REG_SEQ0(LANE_REG(050d), 0x77),
679 REG_SEQ0(LANE_REG(050e), 0x38),
680 REG_SEQ0(LANE_REG(0510), 0x03),
681 REG_SEQ0(LANE_REG(0511), 0x0f),
682 REG_SEQ0(LANE_REG(0516), 0x02),
683 REG_SEQ0(LANE_REG(051b), 0x01),
684 REG_SEQ0(LANE_REG(051f), 0x15),
685 REG_SEQ0(LANE_REG(0520), 0xa0),
686 REG_SEQ0(LANE_REG(0603), 0x0c),
687 REG_SEQ0(LANE_REG(0607), 0x20),
688 REG_SEQ0(LANE_REG(060a), 0x17),
689 REG_SEQ0(LANE_REG(060b), 0x77),
690 REG_SEQ0(LANE_REG(060c), 0x77),
691 REG_SEQ0(LANE_REG(060d), 0x77),
692 REG_SEQ0(LANE_REG(060e), 0x38),
693 REG_SEQ0(LANE_REG(0610), 0x03),
694 REG_SEQ0(LANE_REG(0611), 0x0f),
695 REG_SEQ0(LANE_REG(0616), 0x02),
696 REG_SEQ0(LANE_REG(061b), 0x01),
697 REG_SEQ0(LANE_REG(061f), 0x15),
698 REG_SEQ0(LANE_REG(0620), 0xa0),
699 };
700
701 static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = {
702 REG_SEQ0(LANE_REG(0312), 0x00),
703 REG_SEQ0(LANE_REG(031e), 0x00),
704 REG_SEQ0(LANE_REG(0412), 0x00),
705 REG_SEQ0(LANE_REG(041e), 0x00),
706 REG_SEQ0(LANE_REG(0512), 0x00),
707 REG_SEQ0(LANE_REG(051e), 0x00),
708 REG_SEQ0(LANE_REG(0612), 0x00),
709 REG_SEQ0(LANE_REG(061e), 0x08),
710 REG_SEQ0(LANE_REG(0303), 0x2f),
711 REG_SEQ0(LANE_REG(0403), 0x2f),
712 REG_SEQ0(LANE_REG(0503), 0x2f),
713 REG_SEQ0(LANE_REG(0603), 0x2f),
714 REG_SEQ0(LANE_REG(0305), 0x03),
715 REG_SEQ0(LANE_REG(0405), 0x03),
716 REG_SEQ0(LANE_REG(0505), 0x03),
717 REG_SEQ0(LANE_REG(0605), 0x03),
718 REG_SEQ0(LANE_REG(0306), 0x1c),
719 REG_SEQ0(LANE_REG(0406), 0x1c),
720 REG_SEQ0(LANE_REG(0506), 0x1c),
721 REG_SEQ0(LANE_REG(0606), 0x1c),
722 };
723
724 static struct tx_drv_ctrl tx_drv_ctrl_rbr[4][4] = {
725 /* voltage swing 0, pre-emphasis 0->3 */
726 {
727 { 0x2, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
728 { 0x4, 0x3, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
729 { 0x7, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
730 { 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
731 },
732
733 /* voltage swing 1, pre-emphasis 0->2 */
734 {
735 { 0x4, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
736 { 0x9, 0x5, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
737 { 0xc, 0x8, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
738 },
739
740 /* voltage swing 2, pre-emphasis 0->1 */
741 {
742 { 0x8, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
743 { 0xc, 0x5, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
744 },
745
746 /* voltage swing 3, pre-emphasis 0 */
747 {
748 { 0xb, 0x0, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 },
749 }
750 };
751
752 static struct tx_drv_ctrl tx_drv_ctrl_hbr[4][4] = {
753 /* voltage swing 0, pre-emphasis 0->3 */
754 {
755 { 0x2, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
756 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
757 { 0x9, 0x8, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
758 { 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
759 },
760
761 /* voltage swing 1, pre-emphasis 0->2 */
762 {
763 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
764 { 0xa, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
765 { 0xc, 0x8, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
766 },
767
768 /* voltage swing 2, pre-emphasis 0->1 */
769 {
770 { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
771 { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
772 },
773
774 /* voltage swing 3, pre-emphasis 0 */
775 {
776 { 0xc, 0x1, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 },
777 }
778 };
779
780 static struct tx_drv_ctrl tx_drv_ctrl_hbr2[4][4] = {
781 /* voltage swing 0, pre-emphasis 0->3 */
782 {
783 { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
784 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
785 { 0x9, 0x8, 0x4, 0x6, 0x1, 0x4, 0x0, 0x1, 0x7, 0x7 },
786 { 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
787 },
788
789 /* voltage swing 1, pre-emphasis 0->2 */
790 {
791 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
792 { 0xb, 0x7, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 },
793 { 0xd, 0x9, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
794 },
795
796 /* voltage swing 2, pre-emphasis 0->1 */
797 {
798 { 0x8, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 },
799 { 0xc, 0x6, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 },
800 },
801
802 /* voltage swing 3, pre-emphasis 0 */
803 {
804 { 0xb, 0x0, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 },
805 }
806 };
807
rk_hdptx_phy_is_rw_reg(struct device * dev,unsigned int reg)808 static bool rk_hdptx_phy_is_rw_reg(struct device *dev, unsigned int reg)
809 {
810 switch (reg) {
811 case 0x0000 ... 0x029c: /* CMN Register */
812 case 0x0400 ... 0x04a4: /* Sideband Register */
813 case 0x0800 ... 0x08a4: /* Lane Top Register */
814 case 0x0c00 ... 0x0cb4: /* Lane 0 Register */
815 case 0x1000 ... 0x10b4: /* Lane 1 Register */
816 case 0x1400 ... 0x14b4: /* Lane 2 Register */
817 case 0x1800 ... 0x18b4: /* Lane 3 Register */
818 return true;
819 }
820
821 return false;
822 }
823
824 static const struct regmap_config rk_hdptx_phy_regmap_config = {
825 .reg_bits = 32,
826 .reg_stride = 4,
827 .val_bits = 32,
828 .writeable_reg = rk_hdptx_phy_is_rw_reg,
829 .readable_reg = rk_hdptx_phy_is_rw_reg,
830 .fast_io = true,
831 .max_register = 0x18b4,
832 };
833
834 #define rk_hdptx_multi_reg_write(hdptx, seq) \
835 regmap_multi_reg_write((hdptx)->regmap, seq, ARRAY_SIZE(seq))
836
rk_hdptx_pre_power_up(struct rk_hdptx_phy * hdptx)837 static void rk_hdptx_pre_power_up(struct rk_hdptx_phy *hdptx)
838 {
839 u32 val;
840
841 reset_control_assert(hdptx->rsts[RST_APB].rstc);
842 usleep_range(20, 25);
843 reset_control_deassert(hdptx->rsts[RST_APB].rstc);
844
845 reset_control_assert(hdptx->rsts[RST_LANE].rstc);
846 reset_control_assert(hdptx->rsts[RST_CMN].rstc);
847 reset_control_assert(hdptx->rsts[RST_INIT].rstc);
848
849 val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16;
850 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
851 }
852
rk_hdptx_post_enable_lane(struct rk_hdptx_phy * hdptx)853 static int rk_hdptx_post_enable_lane(struct rk_hdptx_phy *hdptx)
854 {
855 u32 val;
856 int ret;
857
858 reset_control_deassert(hdptx->rsts[RST_LANE].rstc);
859
860 val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 |
861 HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN;
862 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
863
864 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val,
865 (val & HDPTX_O_PHY_RDY) &&
866 (val & HDPTX_O_PLL_LOCK_DONE),
867 100, 5000);
868 if (ret) {
869 dev_err(hdptx->dev, "Failed to get PHY lane lock: %d\n", ret);
870 return ret;
871 }
872
873 dev_dbg(hdptx->dev, "PHY lane locked\n");
874
875 return 0;
876 }
877
rk_hdptx_post_enable_pll(struct rk_hdptx_phy * hdptx)878 static int rk_hdptx_post_enable_pll(struct rk_hdptx_phy *hdptx)
879 {
880 u32 val;
881 int ret;
882
883 val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 |
884 HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN;
885 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
886
887 usleep_range(10, 15);
888 reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
889
890 usleep_range(10, 15);
891 val = HDPTX_I_PLL_EN << 16 | HDPTX_I_PLL_EN;
892 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
893
894 usleep_range(10, 15);
895 reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
896
897 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val,
898 val & HDPTX_O_PHY_CLK_RDY, 20, 400);
899 if (ret) {
900 dev_err(hdptx->dev, "Failed to get PHY clk ready: %d\n", ret);
901 return ret;
902 }
903
904 dev_dbg(hdptx->dev, "PHY clk ready\n");
905
906 return 0;
907 }
908
rk_hdptx_phy_disable(struct rk_hdptx_phy * hdptx)909 static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx)
910 {
911 u32 val;
912
913 reset_control_assert(hdptx->rsts[RST_APB].rstc);
914 usleep_range(20, 30);
915 reset_control_deassert(hdptx->rsts[RST_APB].rstc);
916
917 regmap_write(hdptx->regmap, LANE_REG(0300), 0x82);
918 regmap_write(hdptx->regmap, SB_REG(010f), 0xc1);
919 regmap_write(hdptx->regmap, SB_REG(0110), 0x1);
920 regmap_write(hdptx->regmap, LANE_REG(0301), 0x80);
921 regmap_write(hdptx->regmap, LANE_REG(0401), 0x80);
922 regmap_write(hdptx->regmap, LANE_REG(0501), 0x80);
923 regmap_write(hdptx->regmap, LANE_REG(0601), 0x80);
924
925 reset_control_assert(hdptx->rsts[RST_LANE].rstc);
926 reset_control_assert(hdptx->rsts[RST_CMN].rstc);
927 reset_control_assert(hdptx->rsts[RST_INIT].rstc);
928
929 val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16;
930 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val);
931 }
932
rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,struct ropll_config * cfg)933 static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate,
934 struct ropll_config *cfg)
935 {
936 const unsigned int fout = data_rate / 2, fref = 24000;
937 unsigned long k = 0, lc, k_sub, lc_sub;
938 unsigned int fvco, sdc;
939 u32 mdiv, sdiv, n = 8;
940
941 if (fout > 0xfffffff)
942 return false;
943
944 for (sdiv = 16; sdiv >= 1; sdiv--) {
945 if (sdiv % 2 && sdiv != 1)
946 continue;
947
948 fvco = fout * sdiv;
949
950 if (fvco < 2000000 || fvco > 4000000)
951 continue;
952
953 mdiv = DIV_ROUND_UP(fvco, fref);
954 if (mdiv < 20 || mdiv > 255)
955 continue;
956
957 if (fref * mdiv - fvco) {
958 for (sdc = 264000; sdc <= 750000; sdc += fref)
959 if (sdc * n > fref * mdiv)
960 break;
961
962 if (sdc > 750000)
963 continue;
964
965 rational_best_approximation(fref * mdiv - fvco,
966 sdc / 16,
967 GENMASK(6, 0),
968 GENMASK(7, 0),
969 &k, &lc);
970
971 rational_best_approximation(sdc * n - fref * mdiv,
972 sdc,
973 GENMASK(6, 0),
974 GENMASK(7, 0),
975 &k_sub, &lc_sub);
976 }
977
978 break;
979 }
980
981 if (sdiv < 1)
982 return false;
983
984 if (cfg) {
985 cfg->pms_mdiv = mdiv;
986 cfg->pms_mdiv_afc = mdiv;
987 cfg->pms_pdiv = 1;
988 cfg->pms_refdiv = 1;
989 cfg->pms_sdiv = sdiv - 1;
990
991 cfg->sdm_en = k > 0 ? 1 : 0;
992 if (cfg->sdm_en) {
993 cfg->sdm_deno = lc;
994 cfg->sdm_num_sign = 1;
995 cfg->sdm_num = k;
996 cfg->sdc_n = n - 3;
997 cfg->sdc_num = k_sub;
998 cfg->sdc_deno = lc_sub;
999 }
1000 }
1001
1002 return true;
1003 }
1004
rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy * hdptx,unsigned int rate)1005 static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx,
1006 unsigned int rate)
1007 {
1008 const struct ropll_config *cfg = NULL;
1009 struct ropll_config rc = {0};
1010 int i;
1011
1012 hdptx->rate = rate * 100;
1013
1014 for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
1015 if (rate == ropll_tmds_cfg[i].bit_rate) {
1016 cfg = &ropll_tmds_cfg[i];
1017 break;
1018 }
1019
1020 if (!cfg) {
1021 if (rk_hdptx_phy_clk_pll_calc(rate, &rc)) {
1022 cfg = &rc;
1023 } else {
1024 dev_err(hdptx->dev, "%s cannot find pll cfg\n", __func__);
1025 return -EINVAL;
1026 }
1027 }
1028
1029 dev_dbg(hdptx->dev, "mdiv=%u, sdiv=%u, sdm_en=%u, k_sign=%u, k=%u, lc=%u\n",
1030 cfg->pms_mdiv, cfg->pms_sdiv + 1, cfg->sdm_en,
1031 cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno);
1032
1033 rk_hdptx_pre_power_up(hdptx);
1034
1035 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq);
1036 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_cmn_init_seq);
1037
1038 regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv);
1039 regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc);
1040 regmap_write(hdptx->regmap, CMN_REG(0059),
1041 (cfg->pms_pdiv << 4) | cfg->pms_refdiv);
1042 regmap_write(hdptx->regmap, CMN_REG(005a), cfg->pms_sdiv << 4);
1043
1044 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK,
1045 FIELD_PREP(ROPLL_SDM_EN_MASK, cfg->sdm_en));
1046 if (!cfg->sdm_en)
1047 regmap_update_bits(hdptx->regmap, CMN_REG(005e), 0xf, 0);
1048
1049 regmap_update_bits(hdptx->regmap, CMN_REG(0064), ROPLL_SDM_NUM_SIGN_RBR_MASK,
1050 FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, cfg->sdm_num_sign));
1051
1052 regmap_write(hdptx->regmap, CMN_REG(0060), cfg->sdm_deno);
1053 regmap_write(hdptx->regmap, CMN_REG(0065), cfg->sdm_num);
1054
1055 regmap_update_bits(hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK,
1056 FIELD_PREP(ROPLL_SDC_N_RBR_MASK, cfg->sdc_n));
1057
1058 regmap_write(hdptx->regmap, CMN_REG(006c), cfg->sdc_num);
1059 regmap_write(hdptx->regmap, CMN_REG(0070), cfg->sdc_deno);
1060
1061 regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK,
1062 FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv));
1063
1064 regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN_MASK,
1065 FIELD_PREP(PLL_PCG_CLK_EN_MASK, 0x1));
1066
1067 return rk_hdptx_post_enable_pll(hdptx);
1068 }
1069
rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy * hdptx,unsigned int rate)1070 static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx,
1071 unsigned int rate)
1072 {
1073 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq);
1074
1075 regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06);
1076
1077 if (rate >= 3400000) {
1078 /* For 1/40 bitrate clk */
1079 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq);
1080 } else {
1081 /* For 1/10 bitrate clk */
1082 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_lowbr_seq);
1083 }
1084
1085 regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07);
1086 regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f);
1087
1088 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq);
1089 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq);
1090
1091 return rk_hdptx_post_enable_lane(hdptx);
1092 }
1093
rk_hdptx_dp_reset(struct rk_hdptx_phy * hdptx)1094 static void rk_hdptx_dp_reset(struct rk_hdptx_phy *hdptx)
1095 {
1096 reset_control_assert(hdptx->rsts[RST_LANE].rstc);
1097 reset_control_assert(hdptx->rsts[RST_CMN].rstc);
1098 reset_control_assert(hdptx->rsts[RST_INIT].rstc);
1099
1100 reset_control_assert(hdptx->rsts[RST_APB].rstc);
1101 udelay(10);
1102 reset_control_deassert(hdptx->rsts[RST_APB].rstc);
1103
1104 regmap_update_bits(hdptx->regmap, LANE_REG(0301),
1105 OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK,
1106 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) |
1107 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0));
1108 regmap_update_bits(hdptx->regmap, LANE_REG(0401),
1109 OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK,
1110 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) |
1111 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0));
1112 regmap_update_bits(hdptx->regmap, LANE_REG(0501),
1113 OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK,
1114 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) |
1115 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0));
1116 regmap_update_bits(hdptx->regmap, LANE_REG(0601),
1117 OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK,
1118 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) |
1119 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0));
1120
1121 regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1122 HDPTX_I_PLL_EN << 16 | FIELD_PREP(HDPTX_I_PLL_EN, 0x0));
1123 regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1124 HDPTX_I_BIAS_EN << 16 | FIELD_PREP(HDPTX_I_BIAS_EN, 0x0));
1125 regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1126 HDPTX_I_BGR_EN << 16 | FIELD_PREP(HDPTX_I_BGR_EN, 0x0));
1127 }
1128
rk_hdptx_phy_consumer_get(struct rk_hdptx_phy * hdptx,unsigned int rate)1129 static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx,
1130 unsigned int rate)
1131 {
1132 enum phy_mode mode = phy_get_mode(hdptx->phy);
1133 u32 status;
1134 int ret;
1135
1136 if (atomic_inc_return(&hdptx->usage_count) > 1)
1137 return 0;
1138
1139 ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status);
1140 if (ret)
1141 goto dec_usage;
1142
1143 if (status & HDPTX_O_PLL_LOCK_DONE)
1144 dev_warn(hdptx->dev, "PLL locked by unknown consumer!\n");
1145
1146 if (mode == PHY_MODE_DP) {
1147 rk_hdptx_dp_reset(hdptx);
1148 } else {
1149 if (rate) {
1150 ret = rk_hdptx_ropll_tmds_cmn_config(hdptx, rate);
1151 if (ret)
1152 goto dec_usage;
1153 }
1154 }
1155
1156 return 0;
1157
1158 dec_usage:
1159 atomic_dec(&hdptx->usage_count);
1160 return ret;
1161 }
1162
rk_hdptx_phy_consumer_put(struct rk_hdptx_phy * hdptx,bool force)1163 static int rk_hdptx_phy_consumer_put(struct rk_hdptx_phy *hdptx, bool force)
1164 {
1165 enum phy_mode mode = phy_get_mode(hdptx->phy);
1166 u32 status;
1167 int ret;
1168
1169 ret = atomic_dec_return(&hdptx->usage_count);
1170 if (ret > 0)
1171 return 0;
1172
1173 if (ret < 0) {
1174 dev_warn(hdptx->dev, "Usage count underflow!\n");
1175 ret = -EINVAL;
1176 } else {
1177 ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status);
1178 if (!ret) {
1179 if (status & HDPTX_O_PLL_LOCK_DONE) {
1180 if (mode == PHY_MODE_DP)
1181 rk_hdptx_dp_reset(hdptx);
1182 else
1183 rk_hdptx_phy_disable(hdptx);
1184 }
1185 return 0;
1186 } else if (force) {
1187 return 0;
1188 }
1189 }
1190
1191 atomic_inc(&hdptx->usage_count);
1192 return ret;
1193 }
1194
rk_hdptx_dp_pll_init(struct rk_hdptx_phy * hdptx)1195 static void rk_hdptx_dp_pll_init(struct rk_hdptx_phy *hdptx)
1196 {
1197 regmap_update_bits(hdptx->regmap, CMN_REG(003c), ANA_LCPLL_RESERVED7_MASK,
1198 FIELD_PREP(ANA_LCPLL_RESERVED7_MASK, 0x1));
1199
1200 regmap_update_bits(hdptx->regmap, CMN_REG(0046),
1201 ROPLL_ANA_CPP_CTRL_COARSE_MASK | ROPLL_ANA_CPP_CTRL_FINE_MASK,
1202 FIELD_PREP(ROPLL_ANA_CPP_CTRL_COARSE_MASK, 0xe) |
1203 FIELD_PREP(ROPLL_ANA_CPP_CTRL_FINE_MASK, 0xe));
1204 regmap_update_bits(hdptx->regmap, CMN_REG(0047),
1205 ROPLL_ANA_LPF_C_SEL_COARSE_MASK |
1206 ROPLL_ANA_LPF_C_SEL_FINE_MASK,
1207 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_COARSE_MASK, 0x4) |
1208 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_FINE_MASK, 0x4));
1209
1210 regmap_write(hdptx->regmap, CMN_REG(0051), FIELD_PREP(ROPLL_PMS_MDIV_MASK, 0x87));
1211 regmap_write(hdptx->regmap, CMN_REG(0052), FIELD_PREP(ROPLL_PMS_MDIV_MASK, 0x71));
1212 regmap_write(hdptx->regmap, CMN_REG(0053), FIELD_PREP(ROPLL_PMS_MDIV_MASK, 0x71));
1213
1214 regmap_write(hdptx->regmap, CMN_REG(0055),
1215 FIELD_PREP(ROPLL_PMS_MDIV_AFC_MASK, 0x87));
1216 regmap_write(hdptx->regmap, CMN_REG(0056),
1217 FIELD_PREP(ROPLL_PMS_MDIV_AFC_MASK, 0x71));
1218 regmap_write(hdptx->regmap, CMN_REG(0057),
1219 FIELD_PREP(ROPLL_PMS_MDIV_AFC_MASK, 0x71));
1220
1221 regmap_write(hdptx->regmap, CMN_REG(0059),
1222 FIELD_PREP(ANA_ROPLL_PMS_PDIV_MASK, 0x1) |
1223 FIELD_PREP(ANA_ROPLL_PMS_REFDIV_MASK, 0x1));
1224 regmap_write(hdptx->regmap, CMN_REG(005a),
1225 FIELD_PREP(ROPLL_PMS_SDIV_RBR_MASK, 0x3) |
1226 FIELD_PREP(ROPLL_PMS_SDIV_HBR_MASK, 0x1));
1227 regmap_update_bits(hdptx->regmap, CMN_REG(005b), ROPLL_PMS_SDIV_HBR2_MASK,
1228 FIELD_PREP(ROPLL_PMS_SDIV_HBR2_MASK, 0x0));
1229
1230 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK,
1231 FIELD_PREP(ROPLL_SDM_EN_MASK, 0x1));
1232 regmap_update_bits(hdptx->regmap, CMN_REG(005e),
1233 OVRD_ROPLL_SDM_RSTN_MASK | ROPLL_SDM_RSTN_MASK,
1234 FIELD_PREP(OVRD_ROPLL_SDM_RSTN_MASK, 0x1) |
1235 FIELD_PREP(ROPLL_SDM_RSTN_MASK, 0x1));
1236 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDC_FRAC_EN_RBR_MASK,
1237 FIELD_PREP(ROPLL_SDC_FRAC_EN_RBR_MASK, 0x1));
1238 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDC_FRAC_EN_HBR_MASK,
1239 FIELD_PREP(ROPLL_SDC_FRAC_EN_HBR_MASK, 0x1));
1240 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDC_FRAC_EN_HBR2_MASK,
1241 FIELD_PREP(ROPLL_SDC_FRAC_EN_HBR2_MASK, 0x1));
1242
1243 regmap_update_bits(hdptx->regmap, CMN_REG(005f),
1244 OVRD_ROPLL_SDC_RSTN_MASK | ROPLL_SDC_RSTN_MASK,
1245 FIELD_PREP(OVRD_ROPLL_SDC_RSTN_MASK, 0x1) |
1246 FIELD_PREP(ROPLL_SDC_RSTN_MASK, 0x1));
1247 regmap_write(hdptx->regmap, CMN_REG(0060),
1248 FIELD_PREP(ROPLL_SDM_DENOMINATOR_MASK, 0x21));
1249 regmap_write(hdptx->regmap, CMN_REG(0061),
1250 FIELD_PREP(ROPLL_SDM_DENOMINATOR_MASK, 0x27));
1251 regmap_write(hdptx->regmap, CMN_REG(0062),
1252 FIELD_PREP(ROPLL_SDM_DENOMINATOR_MASK, 0x27));
1253
1254 regmap_update_bits(hdptx->regmap, CMN_REG(0064),
1255 ROPLL_SDM_NUM_SIGN_RBR_MASK |
1256 ROPLL_SDM_NUM_SIGN_HBR_MASK |
1257 ROPLL_SDM_NUM_SIGN_HBR2_MASK,
1258 FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, 0x0) |
1259 FIELD_PREP(ROPLL_SDM_NUM_SIGN_HBR_MASK, 0x1) |
1260 FIELD_PREP(ROPLL_SDM_NUM_SIGN_HBR2_MASK, 0x1));
1261 regmap_write(hdptx->regmap, CMN_REG(0065),
1262 FIELD_PREP(ROPLL_SDM_NUM_MASK, 0x0));
1263 regmap_write(hdptx->regmap, CMN_REG(0066),
1264 FIELD_PREP(ROPLL_SDM_NUM_MASK, 0xd));
1265 regmap_write(hdptx->regmap, CMN_REG(0067),
1266 FIELD_PREP(ROPLL_SDM_NUM_MASK, 0xd));
1267
1268 regmap_update_bits(hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK,
1269 FIELD_PREP(ROPLL_SDC_N_RBR_MASK, 0x2));
1270
1271 regmap_update_bits(hdptx->regmap, CMN_REG(006a),
1272 ROPLL_SDC_N_HBR_MASK | ROPLL_SDC_N_HBR2_MASK,
1273 FIELD_PREP(ROPLL_SDC_N_HBR_MASK, 0x1) |
1274 FIELD_PREP(ROPLL_SDC_N_HBR2_MASK, 0x1));
1275
1276 regmap_write(hdptx->regmap, CMN_REG(006c),
1277 FIELD_PREP(ROPLL_SDC_NUM_MASK, 0x3));
1278 regmap_write(hdptx->regmap, CMN_REG(006d),
1279 FIELD_PREP(ROPLL_SDC_NUM_MASK, 0x7));
1280 regmap_write(hdptx->regmap, CMN_REG(006e),
1281 FIELD_PREP(ROPLL_SDC_NUM_MASK, 0x7));
1282
1283 regmap_write(hdptx->regmap, CMN_REG(0070),
1284 FIELD_PREP(ROPLL_SDC_DENO_MASK, 0x8));
1285 regmap_write(hdptx->regmap, CMN_REG(0071),
1286 FIELD_PREP(ROPLL_SDC_DENO_MASK, 0x18));
1287 regmap_write(hdptx->regmap, CMN_REG(0072),
1288 FIELD_PREP(ROPLL_SDC_DENO_MASK, 0x18));
1289
1290 regmap_update_bits(hdptx->regmap, CMN_REG(0074),
1291 OVRD_ROPLL_SDC_NDIV_RSTN_MASK | ROPLL_SDC_NDIV_RSTN_MASK,
1292 FIELD_PREP(OVRD_ROPLL_SDC_NDIV_RSTN_MASK, 0x1) |
1293 FIELD_PREP(ROPLL_SDC_NDIV_RSTN_MASK, 0x1));
1294
1295 regmap_update_bits(hdptx->regmap, CMN_REG(0077), ANA_ROPLL_SSC_CLK_DIV_SEL_MASK,
1296 FIELD_PREP(ANA_ROPLL_SSC_CLK_DIV_SEL_MASK, 0x1));
1297
1298 regmap_update_bits(hdptx->regmap, CMN_REG(0081), ANA_PLL_CD_TX_SER_RATE_SEL_MASK,
1299 FIELD_PREP(ANA_PLL_CD_TX_SER_RATE_SEL_MASK, 0x0));
1300 regmap_update_bits(hdptx->regmap, CMN_REG(0081),
1301 ANA_PLL_CD_HSCLK_EAST_EN_MASK | ANA_PLL_CD_HSCLK_WEST_EN_MASK,
1302 FIELD_PREP(ANA_PLL_CD_HSCLK_EAST_EN_MASK, 0x1) |
1303 FIELD_PREP(ANA_PLL_CD_HSCLK_WEST_EN_MASK, 0x0));
1304
1305 regmap_update_bits(hdptx->regmap, CMN_REG(0082), ANA_PLL_CD_VREG_GAIN_CTRL_MASK,
1306 FIELD_PREP(ANA_PLL_CD_VREG_GAIN_CTRL_MASK, 0x4));
1307 regmap_update_bits(hdptx->regmap, CMN_REG(0083), ANA_PLL_CD_VREG_ICTRL_MASK,
1308 FIELD_PREP(ANA_PLL_CD_VREG_ICTRL_MASK, 0x1));
1309 regmap_update_bits(hdptx->regmap, CMN_REG(0084), PLL_LCRO_CLK_SEL_MASK,
1310 FIELD_PREP(PLL_LCRO_CLK_SEL_MASK, 0x1));
1311 regmap_update_bits(hdptx->regmap, CMN_REG(0085), ANA_PLL_SYNC_LOSS_DET_MODE_MASK,
1312 FIELD_PREP(ANA_PLL_SYNC_LOSS_DET_MODE_MASK, 0x3));
1313
1314 regmap_update_bits(hdptx->regmap, CMN_REG(0087), ANA_PLL_TX_HS_CLK_EN_MASK,
1315 FIELD_PREP(ANA_PLL_TX_HS_CLK_EN_MASK, 0x1));
1316
1317 regmap_update_bits(hdptx->regmap, CMN_REG(0097), DIG_CLK_SEL_MASK,
1318 FIELD_PREP(DIG_CLK_SEL_MASK, 0x1));
1319
1320 regmap_update_bits(hdptx->regmap, CMN_REG(0099), CMN_ROPLL_ALONE_MODE_MASK,
1321 FIELD_PREP(CMN_ROPLL_ALONE_MODE_MASK, 0x1));
1322 regmap_update_bits(hdptx->regmap, CMN_REG(009a), HS_SPEED_SEL_MASK,
1323 FIELD_PREP(HS_SPEED_SEL_MASK, 0x1));
1324 regmap_update_bits(hdptx->regmap, CMN_REG(009b), LS_SPEED_SEL_MASK,
1325 FIELD_PREP(LS_SPEED_SEL_MASK, 0x1));
1326 }
1327
rk_hdptx_dp_aux_init(struct rk_hdptx_phy * hdptx)1328 static int rk_hdptx_dp_aux_init(struct rk_hdptx_phy *hdptx)
1329 {
1330 u32 status;
1331 int ret;
1332
1333 regmap_update_bits(hdptx->regmap, SB_REG(0102), ANA_SB_RXTERM_OFFSP_MASK,
1334 FIELD_PREP(ANA_SB_RXTERM_OFFSP_MASK, 0x3));
1335 regmap_update_bits(hdptx->regmap, SB_REG(0103), ANA_SB_RXTERM_OFFSN_MASK,
1336 FIELD_PREP(ANA_SB_RXTERM_OFFSN_MASK, 0x3));
1337 regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_AUX_EN_MASK,
1338 FIELD_PREP(SB_AUX_EN_MASK, 0x1));
1339 regmap_update_bits(hdptx->regmap, SB_REG(0105), ANA_SB_TX_HLVL_PROG_MASK,
1340 FIELD_PREP(ANA_SB_TX_HLVL_PROG_MASK, 0x7));
1341 regmap_update_bits(hdptx->regmap, SB_REG(0106), ANA_SB_TX_LLVL_PROG_MASK,
1342 FIELD_PREP(ANA_SB_TX_LLVL_PROG_MASK, 0x7));
1343
1344 regmap_update_bits(hdptx->regmap, SB_REG(010d), ANA_SB_DMRX_LPBK_DATA_MASK,
1345 FIELD_PREP(ANA_SB_DMRX_LPBK_DATA_MASK, 0x1));
1346
1347 regmap_update_bits(hdptx->regmap, SB_REG(010f), ANA_SB_VREG_GAIN_CTRL_MASK,
1348 FIELD_PREP(ANA_SB_VREG_GAIN_CTRL_MASK, 0x0));
1349 regmap_update_bits(hdptx->regmap, SB_REG(0110),
1350 ANA_SB_VREG_OUT_SEL_MASK | ANA_SB_VREG_REF_SEL_MASK,
1351 FIELD_PREP(ANA_SB_VREG_OUT_SEL_MASK, 0x1) |
1352 FIELD_PREP(ANA_SB_VREG_REF_SEL_MASK, 0x1));
1353
1354 regmap_update_bits(hdptx->regmap, SB_REG(0113),
1355 SB_RX_RCAL_OPT_CODE_MASK | SB_RX_RTERM_CTRL_MASK,
1356 FIELD_PREP(SB_RX_RCAL_OPT_CODE_MASK, 0x1) |
1357 FIELD_PREP(SB_RX_RTERM_CTRL_MASK, 0x3));
1358 regmap_update_bits(hdptx->regmap, SB_REG(0114),
1359 SB_TG_SB_EN_DELAY_TIME_MASK | SB_TG_RXTERM_EN_DELAY_TIME_MASK,
1360 FIELD_PREP(SB_TG_SB_EN_DELAY_TIME_MASK, 0x2) |
1361 FIELD_PREP(SB_TG_RXTERM_EN_DELAY_TIME_MASK, 0x2));
1362 regmap_update_bits(hdptx->regmap, SB_REG(0115),
1363 SB_READY_DELAY_TIME_MASK | SB_TG_OSC_EN_DELAY_TIME_MASK,
1364 FIELD_PREP(SB_READY_DELAY_TIME_MASK, 0x2) |
1365 FIELD_PREP(SB_TG_OSC_EN_DELAY_TIME_MASK, 0x2));
1366 regmap_update_bits(hdptx->regmap, SB_REG(0116),
1367 AFC_RSTN_DELAY_TIME_MASK,
1368 FIELD_PREP(AFC_RSTN_DELAY_TIME_MASK, 0x2));
1369 regmap_update_bits(hdptx->regmap, SB_REG(0117),
1370 FAST_PULSE_TIME_MASK,
1371 FIELD_PREP(FAST_PULSE_TIME_MASK, 0x4));
1372 regmap_update_bits(hdptx->regmap, SB_REG(0118),
1373 SB_TG_EARC_DMRX_RECVRD_CLK_CNT_MASK,
1374 FIELD_PREP(SB_TG_EARC_DMRX_RECVRD_CLK_CNT_MASK, 0xa));
1375
1376 regmap_update_bits(hdptx->regmap, SB_REG(011a), SB_TG_CNT_RUN_NO_7_0_MASK,
1377 FIELD_PREP(SB_TG_CNT_RUN_NO_7_0_MASK, 0x3));
1378 regmap_update_bits(hdptx->regmap, SB_REG(011b),
1379 SB_EARC_SIG_DET_BYPASS_MASK | SB_AFC_TOL_MASK,
1380 FIELD_PREP(SB_EARC_SIG_DET_BYPASS_MASK, 0x1) |
1381 FIELD_PREP(SB_AFC_TOL_MASK, 0x3));
1382 regmap_update_bits(hdptx->regmap, SB_REG(011c), SB_AFC_STB_NUM_MASK,
1383 FIELD_PREP(SB_AFC_STB_NUM_MASK, 0x4));
1384 regmap_update_bits(hdptx->regmap, SB_REG(011d), SB_TG_OSC_CNT_MIN_MASK,
1385 FIELD_PREP(SB_TG_OSC_CNT_MIN_MASK, 0x67));
1386 regmap_update_bits(hdptx->regmap, SB_REG(011e), SB_TG_OSC_CNT_MAX_MASK,
1387 FIELD_PREP(SB_TG_OSC_CNT_MAX_MASK, 0x6a));
1388 regmap_update_bits(hdptx->regmap, SB_REG(011f), SB_PWM_AFC_CTRL_MASK,
1389 FIELD_PREP(SB_PWM_AFC_CTRL_MASK, 0x5));
1390 regmap_update_bits(hdptx->regmap, SB_REG(011f), SB_RCAL_RSTN_MASK,
1391 FIELD_PREP(SB_RCAL_RSTN_MASK, 0x1));
1392 regmap_update_bits(hdptx->regmap, SB_REG(0120), SB_AUX_EN_IN_MASK,
1393 FIELD_PREP(SB_AUX_EN_IN_MASK, 0x1));
1394
1395 regmap_update_bits(hdptx->regmap, SB_REG(0102), OVRD_SB_RXTERM_EN_MASK,
1396 FIELD_PREP(OVRD_SB_RXTERM_EN_MASK, 0x1));
1397 regmap_update_bits(hdptx->regmap, SB_REG(0103), OVRD_SB_RX_RESCAL_DONE_MASK,
1398 FIELD_PREP(OVRD_SB_RX_RESCAL_DONE_MASK, 0x1));
1399 regmap_update_bits(hdptx->regmap, SB_REG(0104), OVRD_SB_EN_MASK,
1400 FIELD_PREP(OVRD_SB_EN_MASK, 0x1));
1401 regmap_update_bits(hdptx->regmap, SB_REG(0104), OVRD_SB_AUX_EN_MASK,
1402 FIELD_PREP(OVRD_SB_AUX_EN_MASK, 0x1));
1403
1404 regmap_update_bits(hdptx->regmap, SB_REG(010f), OVRD_SB_VREG_EN_MASK,
1405 FIELD_PREP(OVRD_SB_VREG_EN_MASK, 0x1));
1406
1407 regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1408 HDPTX_I_BGR_EN << 16 | FIELD_PREP(HDPTX_I_BGR_EN, 0x1));
1409 regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1410 HDPTX_I_BIAS_EN << 16 | FIELD_PREP(HDPTX_I_BIAS_EN, 0x1));
1411 usleep_range(20, 25);
1412
1413 reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
1414 usleep_range(20, 25);
1415 reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
1416 usleep_range(20, 25);
1417
1418 regmap_update_bits(hdptx->regmap, SB_REG(0103), OVRD_SB_RX_RESCAL_DONE_MASK,
1419 FIELD_PREP(OVRD_SB_RX_RESCAL_DONE_MASK, 0x1));
1420 usleep_range(100, 110);
1421 regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_EN_MASK,
1422 FIELD_PREP(SB_EN_MASK, 0x1));
1423 usleep_range(100, 110);
1424 regmap_update_bits(hdptx->regmap, SB_REG(0102), SB_RXTERM_EN_MASK,
1425 FIELD_PREP(SB_RXTERM_EN_MASK, 0x1));
1426 usleep_range(20, 25);
1427 regmap_update_bits(hdptx->regmap, SB_REG(010f), SB_VREG_EN_MASK,
1428 FIELD_PREP(SB_VREG_EN_MASK, 0x1));
1429 usleep_range(20, 25);
1430 regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_AUX_EN_MASK,
1431 FIELD_PREP(SB_AUX_EN_MASK, 0x1));
1432 usleep_range(100, 110);
1433
1434 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS,
1435 status, FIELD_GET(HDPTX_O_SB_RDY, status),
1436 50, 1000);
1437 if (ret) {
1438 dev_err(hdptx->dev, "Failed to get phy sb ready: %d\n", ret);
1439 return ret;
1440 }
1441
1442 return 0;
1443 }
1444
rk_hdptx_phy_power_on(struct phy * phy)1445 static int rk_hdptx_phy_power_on(struct phy *phy)
1446 {
1447 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
1448 int bus_width = phy_get_bus_width(hdptx->phy);
1449 enum phy_mode mode = phy_get_mode(phy);
1450 int ret, lane;
1451
1452 /*
1453 * FIXME: Temporary workaround to pass pixel_clk_rate
1454 * from the HDMI bridge driver until phy_configure_opts_hdmi
1455 * becomes available in the PHY API.
1456 */
1457 unsigned int rate = bus_width & 0xfffffff;
1458
1459 dev_dbg(hdptx->dev, "%s bus_width=%x rate=%u\n",
1460 __func__, bus_width, rate);
1461
1462 ret = rk_hdptx_phy_consumer_get(hdptx, rate);
1463 if (ret)
1464 return ret;
1465
1466 if (mode == PHY_MODE_DP) {
1467 regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1468 HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x1));
1469
1470 for (lane = 0; lane < 4; lane++) {
1471 regmap_update_bits(hdptx->regmap, LANE_REG(031e) + 0x400 * lane,
1472 LN_POLARITY_INV_MASK | LN_LANE_MODE_MASK,
1473 FIELD_PREP(LN_POLARITY_INV_MASK, 0) |
1474 FIELD_PREP(LN_LANE_MODE_MASK, 1));
1475 }
1476
1477 regmap_update_bits(hdptx->regmap, LNTOP_REG(0200), PROTOCOL_SEL_MASK,
1478 FIELD_PREP(PROTOCOL_SEL_MASK, 0x0));
1479 regmap_update_bits(hdptx->regmap, LNTOP_REG(0206), DATA_BUS_WIDTH_MASK,
1480 FIELD_PREP(DATA_BUS_WIDTH_MASK, 0x1));
1481 regmap_update_bits(hdptx->regmap, LNTOP_REG(0206), DATA_BUS_WIDTH_SEL_MASK,
1482 FIELD_PREP(DATA_BUS_WIDTH_SEL_MASK, 0x0));
1483
1484 rk_hdptx_dp_pll_init(hdptx);
1485
1486 ret = rk_hdptx_dp_aux_init(hdptx);
1487 if (ret)
1488 rk_hdptx_phy_consumer_put(hdptx, true);
1489 } else {
1490 regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1491 HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0));
1492
1493 ret = rk_hdptx_ropll_tmds_mode_config(hdptx, rate);
1494 if (ret)
1495 rk_hdptx_phy_consumer_put(hdptx, true);
1496 }
1497
1498 return ret;
1499 }
1500
rk_hdptx_phy_power_off(struct phy * phy)1501 static int rk_hdptx_phy_power_off(struct phy *phy)
1502 {
1503 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
1504
1505 return rk_hdptx_phy_consumer_put(hdptx, false);
1506 }
1507
rk_hdptx_phy_verify_config(struct rk_hdptx_phy * hdptx,struct phy_configure_opts_dp * dp)1508 static int rk_hdptx_phy_verify_config(struct rk_hdptx_phy *hdptx,
1509 struct phy_configure_opts_dp *dp)
1510 {
1511 int i;
1512
1513 if (dp->set_rate) {
1514 switch (dp->link_rate) {
1515 case 1620:
1516 case 2700:
1517 case 5400:
1518 break;
1519 default:
1520 return -EINVAL;
1521 }
1522 }
1523
1524 if (dp->set_lanes) {
1525 switch (dp->lanes) {
1526 case 1:
1527 case 2:
1528 case 4:
1529 break;
1530 default:
1531 return -EINVAL;
1532 }
1533 }
1534
1535 if (dp->set_voltages) {
1536 for (i = 0; i < hdptx->lanes; i++) {
1537 if (dp->voltage[i] > 3 || dp->pre[i] > 3)
1538 return -EINVAL;
1539
1540 if (dp->voltage[i] + dp->pre[i] > 3)
1541 return -EINVAL;
1542 }
1543 }
1544
1545 return 0;
1546 }
1547
rk_hdptx_phy_set_rate(struct rk_hdptx_phy * hdptx,struct phy_configure_opts_dp * dp)1548 static int rk_hdptx_phy_set_rate(struct rk_hdptx_phy *hdptx,
1549 struct phy_configure_opts_dp *dp)
1550 {
1551 u32 bw, status;
1552 int ret;
1553
1554 regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1555 HDPTX_I_PLL_EN << 16 | FIELD_PREP(HDPTX_I_PLL_EN, 0x0));
1556
1557 switch (dp->link_rate) {
1558 case 1620:
1559 bw = DP_BW_RBR;
1560 break;
1561 case 2700:
1562 bw = DP_BW_HBR;
1563 break;
1564 case 5400:
1565 bw = DP_BW_HBR2;
1566 break;
1567 default:
1568 return -EINVAL;
1569 }
1570 hdptx->link_rate = dp->link_rate;
1571
1572 regmap_update_bits(hdptx->regmap, CMN_REG(0008), OVRD_LCPLL_EN_MASK | LCPLL_EN_MASK,
1573 FIELD_PREP(OVRD_LCPLL_EN_MASK, 0x1) |
1574 FIELD_PREP(LCPLL_EN_MASK, 0x0));
1575
1576 regmap_update_bits(hdptx->regmap, CMN_REG(003d), OVRD_ROPLL_EN_MASK | ROPLL_EN_MASK,
1577 FIELD_PREP(OVRD_ROPLL_EN_MASK, 0x1) |
1578 FIELD_PREP(ROPLL_EN_MASK, 0x1));
1579
1580 if (dp->ssc) {
1581 regmap_update_bits(hdptx->regmap, CMN_REG(0074),
1582 OVRD_ROPLL_SSC_EN_MASK | ROPLL_SSC_EN_MASK,
1583 FIELD_PREP(OVRD_ROPLL_SSC_EN_MASK, 0x1) |
1584 FIELD_PREP(ROPLL_SSC_EN_MASK, 0x1));
1585 regmap_write(hdptx->regmap, CMN_REG(0075),
1586 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION_MASK, 0xc));
1587 regmap_update_bits(hdptx->regmap, CMN_REG(0076),
1588 ANA_ROPLL_SSC_FM_FREQ_MASK,
1589 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ_MASK, 0x1f));
1590
1591 regmap_update_bits(hdptx->regmap, CMN_REG(0099), SSC_EN_MASK,
1592 FIELD_PREP(SSC_EN_MASK, 0x2));
1593 } else {
1594 regmap_update_bits(hdptx->regmap, CMN_REG(0074),
1595 OVRD_ROPLL_SSC_EN_MASK | ROPLL_SSC_EN_MASK,
1596 FIELD_PREP(OVRD_ROPLL_SSC_EN_MASK, 0x1) |
1597 FIELD_PREP(ROPLL_SSC_EN_MASK, 0x0));
1598 regmap_write(hdptx->regmap, CMN_REG(0075),
1599 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION_MASK, 0x20));
1600 regmap_update_bits(hdptx->regmap, CMN_REG(0076),
1601 ANA_ROPLL_SSC_FM_FREQ_MASK,
1602 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ_MASK, 0xc));
1603
1604 regmap_update_bits(hdptx->regmap, CMN_REG(0099), SSC_EN_MASK,
1605 FIELD_PREP(SSC_EN_MASK, 0x0));
1606 }
1607
1608 regmap_update_bits(hdptx->regmap, CMN_REG(0095), DP_TX_LINK_BW_MASK,
1609 FIELD_PREP(DP_TX_LINK_BW_MASK, bw));
1610
1611 regmap_write(hdptx->grf, GRF_HDPTX_CON0,
1612 HDPTX_I_PLL_EN << 16 | FIELD_PREP(HDPTX_I_PLL_EN, 0x1));
1613
1614 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS,
1615 status, FIELD_GET(HDPTX_O_PLL_LOCK_DONE, status),
1616 50, 1000);
1617 if (ret) {
1618 dev_err(hdptx->dev, "Failed to get phy pll lock: %d\n", ret);
1619 return ret;
1620 }
1621
1622 return 0;
1623 }
1624
rk_hdptx_phy_set_lanes(struct rk_hdptx_phy * hdptx,struct phy_configure_opts_dp * dp)1625 static int rk_hdptx_phy_set_lanes(struct rk_hdptx_phy *hdptx,
1626 struct phy_configure_opts_dp *dp)
1627 {
1628 hdptx->lanes = dp->lanes;
1629
1630 regmap_update_bits(hdptx->regmap, LNTOP_REG(0207), LANE_EN_MASK,
1631 FIELD_PREP(LANE_EN_MASK, GENMASK(hdptx->lanes - 1, 0)));
1632
1633 return 0;
1634 }
1635
rk_hdptx_phy_set_voltage(struct rk_hdptx_phy * hdptx,struct phy_configure_opts_dp * dp,u8 lane)1636 static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx,
1637 struct phy_configure_opts_dp *dp,
1638 u8 lane)
1639 {
1640 const struct tx_drv_ctrl *ctrl;
1641 u32 offset = lane * 0x400;
1642
1643 switch (hdptx->link_rate) {
1644 case 1620:
1645 ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]];
1646 regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset,
1647 LN_TX_JEQ_EVEN_CTRL_RBR_MASK,
1648 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR_MASK,
1649 ctrl->tx_jeq_even_ctrl));
1650 regmap_update_bits(hdptx->regmap, LANE_REG(030c) + offset,
1651 LN_TX_JEQ_ODD_CTRL_RBR_MASK,
1652 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR_MASK,
1653 ctrl->tx_jeq_odd_ctrl));
1654 regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
1655 LN_TX_SER_40BIT_EN_RBR_MASK,
1656 FIELD_PREP(LN_TX_SER_40BIT_EN_RBR_MASK, 0x1));
1657 break;
1658 case 2700:
1659 ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]];
1660 regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset,
1661 LN_TX_JEQ_EVEN_CTRL_HBR_MASK,
1662 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR_MASK,
1663 ctrl->tx_jeq_even_ctrl));
1664 regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset,
1665 LN_TX_JEQ_ODD_CTRL_HBR_MASK,
1666 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR_MASK,
1667 ctrl->tx_jeq_odd_ctrl));
1668 regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
1669 LN_TX_SER_40BIT_EN_HBR_MASK,
1670 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR_MASK, 0x1));
1671 break;
1672 case 5400:
1673 default:
1674 ctrl = &tx_drv_ctrl_hbr2[dp->voltage[lane]][dp->pre[lane]];
1675 regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset,
1676 LN_TX_JEQ_EVEN_CTRL_HBR2_MASK,
1677 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2_MASK,
1678 ctrl->tx_jeq_even_ctrl));
1679 regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset,
1680 LN_TX_JEQ_ODD_CTRL_HBR2_MASK,
1681 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2_MASK,
1682 ctrl->tx_jeq_odd_ctrl));
1683 regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset,
1684 LN_TX_SER_40BIT_EN_HBR2_MASK,
1685 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2_MASK, 0x1));
1686 break;
1687 }
1688
1689 regmap_update_bits(hdptx->regmap, LANE_REG(0303) + offset,
1690 OVRD_LN_TX_DRV_LVL_CTRL_MASK | LN_TX_DRV_LVL_CTRL_MASK,
1691 FIELD_PREP(OVRD_LN_TX_DRV_LVL_CTRL_MASK, 0x1) |
1692 FIELD_PREP(LN_TX_DRV_LVL_CTRL_MASK,
1693 ctrl->tx_drv_lvl_ctrl));
1694 regmap_update_bits(hdptx->regmap, LANE_REG(0304) + offset,
1695 OVRD_LN_TX_DRV_POST_LVL_CTRL_MASK |
1696 LN_TX_DRV_POST_LVL_CTRL_MASK,
1697 FIELD_PREP(OVRD_LN_TX_DRV_POST_LVL_CTRL_MASK, 0x1) |
1698 FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL_MASK,
1699 ctrl->tx_drv_post_lvl_ctrl));
1700 regmap_update_bits(hdptx->regmap, LANE_REG(0305) + offset,
1701 OVRD_LN_TX_DRV_PRE_LVL_CTRL_MASK |
1702 LN_TX_DRV_PRE_LVL_CTRL_MASK,
1703 FIELD_PREP(OVRD_LN_TX_DRV_PRE_LVL_CTRL_MASK, 0x1) |
1704 FIELD_PREP(LN_TX_DRV_PRE_LVL_CTRL_MASK,
1705 ctrl->tx_drv_pre_lvl_ctrl));
1706 regmap_update_bits(hdptx->regmap, LANE_REG(0306) + offset,
1707 LN_ANA_TX_DRV_IDRV_IDN_CTRL_MASK |
1708 LN_ANA_TX_DRV_IDRV_IUP_CTRL_MASK |
1709 LN_ANA_TX_DRV_ACCDRV_EN_MASK,
1710 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IDN_CTRL_MASK,
1711 ctrl->ana_tx_drv_idrv_idn_ctrl) |
1712 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IUP_CTRL_MASK,
1713 ctrl->ana_tx_drv_idrv_iup_ctrl) |
1714 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_EN_MASK,
1715 ctrl->ana_tx_drv_accdrv_en));
1716 regmap_update_bits(hdptx->regmap, LANE_REG(0307) + offset,
1717 LN_ANA_TX_DRV_ACCDRV_POL_SEL_MASK |
1718 LN_ANA_TX_DRV_ACCDRV_CTRL_MASK,
1719 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_POL_SEL_MASK, 0x1) |
1720 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_CTRL_MASK,
1721 ctrl->ana_tx_drv_accdrv_ctrl));
1722
1723 regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset,
1724 LN_ANA_TX_JEQ_EN_MASK,
1725 FIELD_PREP(LN_ANA_TX_JEQ_EN_MASK, ctrl->ana_tx_jeq_en));
1726
1727 regmap_update_bits(hdptx->regmap, LANE_REG(0310) + offset,
1728 LN_ANA_TX_SYNC_LOSS_DET_MODE_MASK,
1729 FIELD_PREP(LN_ANA_TX_SYNC_LOSS_DET_MODE_MASK, 0x3));
1730
1731 regmap_update_bits(hdptx->regmap, LANE_REG(0316) + offset,
1732 LN_ANA_TX_SER_VREG_GAIN_CTRL_MASK,
1733 FIELD_PREP(LN_ANA_TX_SER_VREG_GAIN_CTRL_MASK, 0x2));
1734
1735 regmap_update_bits(hdptx->regmap, LANE_REG(031b) + offset,
1736 LN_ANA_TX_RESERVED_MASK,
1737 FIELD_PREP(LN_ANA_TX_RESERVED_MASK, 0x1));
1738 }
1739
rk_hdptx_phy_set_voltages(struct rk_hdptx_phy * hdptx,struct phy_configure_opts_dp * dp)1740 static int rk_hdptx_phy_set_voltages(struct rk_hdptx_phy *hdptx,
1741 struct phy_configure_opts_dp *dp)
1742 {
1743 u8 lane;
1744 u32 status;
1745 int ret;
1746
1747 for (lane = 0; lane < hdptx->lanes; lane++)
1748 rk_hdptx_phy_set_voltage(hdptx, dp, lane);
1749
1750 reset_control_deassert(hdptx->rsts[RST_LANE].rstc);
1751
1752 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS,
1753 status, FIELD_GET(HDPTX_O_PHY_RDY, status),
1754 50, 5000);
1755 if (ret) {
1756 dev_err(hdptx->dev, "Failed to get phy ready: %d\n", ret);
1757 return ret;
1758 }
1759
1760 return 0;
1761 }
1762
rk_hdptx_phy_configure(struct phy * phy,union phy_configure_opts * opts)1763 static int rk_hdptx_phy_configure(struct phy *phy, union phy_configure_opts *opts)
1764 {
1765 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy);
1766 enum phy_mode mode = phy_get_mode(phy);
1767 int ret;
1768
1769 if (mode != PHY_MODE_DP)
1770 return 0;
1771
1772 ret = rk_hdptx_phy_verify_config(hdptx, &opts->dp);
1773 if (ret) {
1774 dev_err(hdptx->dev, "invalid params for phy configure\n");
1775 return ret;
1776 }
1777
1778 if (opts->dp.set_rate) {
1779 ret = rk_hdptx_phy_set_rate(hdptx, &opts->dp);
1780 if (ret) {
1781 dev_err(hdptx->dev, "failed to set rate: %d\n", ret);
1782 return ret;
1783 }
1784 }
1785
1786 if (opts->dp.set_lanes) {
1787 ret = rk_hdptx_phy_set_lanes(hdptx, &opts->dp);
1788 if (ret) {
1789 dev_err(hdptx->dev, "failed to set lanes: %d\n", ret);
1790 return ret;
1791 }
1792 }
1793
1794 if (opts->dp.set_voltages) {
1795 ret = rk_hdptx_phy_set_voltages(hdptx, &opts->dp);
1796 if (ret) {
1797 dev_err(hdptx->dev, "failed to set voltages: %d\n",
1798 ret);
1799 return ret;
1800 }
1801 }
1802
1803 return 0;
1804 }
1805
1806 static const struct phy_ops rk_hdptx_phy_ops = {
1807 .power_on = rk_hdptx_phy_power_on,
1808 .power_off = rk_hdptx_phy_power_off,
1809 .configure = rk_hdptx_phy_configure,
1810 .owner = THIS_MODULE,
1811 };
1812
to_rk_hdptx_phy(struct clk_hw * hw)1813 static struct rk_hdptx_phy *to_rk_hdptx_phy(struct clk_hw *hw)
1814 {
1815 return container_of(hw, struct rk_hdptx_phy, hw);
1816 }
1817
rk_hdptx_phy_clk_prepare(struct clk_hw * hw)1818 static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw)
1819 {
1820 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
1821
1822 return rk_hdptx_phy_consumer_get(hdptx, hdptx->rate / 100);
1823 }
1824
rk_hdptx_phy_clk_unprepare(struct clk_hw * hw)1825 static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw)
1826 {
1827 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
1828
1829 rk_hdptx_phy_consumer_put(hdptx, true);
1830 }
1831
rk_hdptx_phy_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1832 static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw,
1833 unsigned long parent_rate)
1834 {
1835 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
1836
1837 return hdptx->rate;
1838 }
1839
rk_hdptx_phy_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)1840 static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
1841 unsigned long *parent_rate)
1842 {
1843 u32 bit_rate = rate / 100;
1844 int i;
1845
1846 if (rate > HDMI20_MAX_RATE)
1847 return rate;
1848
1849 for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++)
1850 if (bit_rate == ropll_tmds_cfg[i].bit_rate)
1851 break;
1852
1853 if (i == ARRAY_SIZE(ropll_tmds_cfg) &&
1854 !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL))
1855 return -EINVAL;
1856
1857 return rate;
1858 }
1859
rk_hdptx_phy_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1860 static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1861 unsigned long parent_rate)
1862 {
1863 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw);
1864
1865 return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100);
1866 }
1867
1868 static const struct clk_ops hdptx_phy_clk_ops = {
1869 .prepare = rk_hdptx_phy_clk_prepare,
1870 .unprepare = rk_hdptx_phy_clk_unprepare,
1871 .recalc_rate = rk_hdptx_phy_clk_recalc_rate,
1872 .round_rate = rk_hdptx_phy_clk_round_rate,
1873 .set_rate = rk_hdptx_phy_clk_set_rate,
1874 };
1875
rk_hdptx_phy_clk_register(struct rk_hdptx_phy * hdptx)1876 static int rk_hdptx_phy_clk_register(struct rk_hdptx_phy *hdptx)
1877 {
1878 struct device *dev = hdptx->dev;
1879 const char *name, *pname;
1880 struct clk *refclk;
1881 int ret;
1882
1883 refclk = devm_clk_get(dev, "ref");
1884 if (IS_ERR(refclk))
1885 return dev_err_probe(dev, PTR_ERR(refclk),
1886 "Failed to get ref clock\n");
1887
1888 name = hdptx->phy_id > 0 ? "clk_hdmiphy_pixel1" : "clk_hdmiphy_pixel0";
1889 pname = __clk_get_name(refclk);
1890
1891 hdptx->hw.init = CLK_HW_INIT(name, pname, &hdptx_phy_clk_ops,
1892 CLK_GET_RATE_NOCACHE);
1893
1894 ret = devm_clk_hw_register(dev, &hdptx->hw);
1895 if (ret)
1896 return dev_err_probe(dev, ret, "Failed to register clock\n");
1897
1898 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &hdptx->hw);
1899 if (ret)
1900 return dev_err_probe(dev, ret,
1901 "Failed to register clk provider\n");
1902 return 0;
1903 }
1904
rk_hdptx_phy_runtime_suspend(struct device * dev)1905 static int rk_hdptx_phy_runtime_suspend(struct device *dev)
1906 {
1907 struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev);
1908
1909 clk_bulk_disable_unprepare(hdptx->nr_clks, hdptx->clks);
1910
1911 return 0;
1912 }
1913
rk_hdptx_phy_runtime_resume(struct device * dev)1914 static int rk_hdptx_phy_runtime_resume(struct device *dev)
1915 {
1916 struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev);
1917 int ret;
1918
1919 ret = clk_bulk_prepare_enable(hdptx->nr_clks, hdptx->clks);
1920 if (ret)
1921 dev_err(hdptx->dev, "Failed to enable clocks: %d\n", ret);
1922
1923 return ret;
1924 }
1925
rk_hdptx_phy_probe(struct platform_device * pdev)1926 static int rk_hdptx_phy_probe(struct platform_device *pdev)
1927 {
1928 struct phy_provider *phy_provider;
1929 struct device *dev = &pdev->dev;
1930 struct rk_hdptx_phy *hdptx;
1931 struct resource *res;
1932 void __iomem *regs;
1933 int ret, id;
1934
1935 hdptx = devm_kzalloc(dev, sizeof(*hdptx), GFP_KERNEL);
1936 if (!hdptx)
1937 return -ENOMEM;
1938
1939 hdptx->dev = dev;
1940
1941 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1942 if (IS_ERR(regs))
1943 return dev_err_probe(dev, PTR_ERR(regs),
1944 "Failed to ioremap resource\n");
1945
1946 hdptx->cfgs = device_get_match_data(dev);
1947 if (!hdptx->cfgs)
1948 return dev_err_probe(dev, -EINVAL, "missing match data\n");
1949
1950 /* find the phy-id from the io address */
1951 hdptx->phy_id = -ENODEV;
1952 for (id = 0; id < hdptx->cfgs->num_phys; id++) {
1953 if (res->start == hdptx->cfgs->phy_ids[id]) {
1954 hdptx->phy_id = id;
1955 break;
1956 }
1957 }
1958
1959 if (hdptx->phy_id < 0)
1960 return dev_err_probe(dev, -ENODEV, "no matching device found\n");
1961
1962 ret = devm_clk_bulk_get_all(dev, &hdptx->clks);
1963 if (ret < 0)
1964 return dev_err_probe(dev, ret, "Failed to get clocks\n");
1965 if (ret == 0)
1966 return dev_err_probe(dev, -EINVAL, "Missing clocks\n");
1967
1968 hdptx->nr_clks = ret;
1969
1970 hdptx->regmap = devm_regmap_init_mmio(dev, regs,
1971 &rk_hdptx_phy_regmap_config);
1972 if (IS_ERR(hdptx->regmap))
1973 return dev_err_probe(dev, PTR_ERR(hdptx->regmap),
1974 "Failed to init regmap\n");
1975
1976 hdptx->rsts[RST_APB].id = "apb";
1977 hdptx->rsts[RST_INIT].id = "init";
1978 hdptx->rsts[RST_CMN].id = "cmn";
1979 hdptx->rsts[RST_LANE].id = "lane";
1980
1981 ret = devm_reset_control_bulk_get_exclusive(dev, RST_MAX, hdptx->rsts);
1982 if (ret)
1983 return dev_err_probe(dev, ret, "Failed to get resets\n");
1984
1985 hdptx->grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1986 "rockchip,grf");
1987 if (IS_ERR(hdptx->grf))
1988 return dev_err_probe(dev, PTR_ERR(hdptx->grf),
1989 "Could not get GRF syscon\n");
1990
1991 platform_set_drvdata(pdev, hdptx);
1992
1993 ret = devm_pm_runtime_enable(dev);
1994 if (ret)
1995 return dev_err_probe(dev, ret, "Failed to enable runtime PM\n");
1996
1997 hdptx->phy = devm_phy_create(dev, NULL, &rk_hdptx_phy_ops);
1998 if (IS_ERR(hdptx->phy))
1999 return dev_err_probe(dev, PTR_ERR(hdptx->phy),
2000 "Failed to create HDMI PHY\n");
2001
2002 phy_set_drvdata(hdptx->phy, hdptx);
2003 phy_set_bus_width(hdptx->phy, 8);
2004
2005 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2006 if (IS_ERR(phy_provider))
2007 return dev_err_probe(dev, PTR_ERR(phy_provider),
2008 "Failed to register PHY provider\n");
2009
2010 reset_control_deassert(hdptx->rsts[RST_APB].rstc);
2011 reset_control_deassert(hdptx->rsts[RST_CMN].rstc);
2012 reset_control_deassert(hdptx->rsts[RST_INIT].rstc);
2013
2014 return rk_hdptx_phy_clk_register(hdptx);
2015 }
2016
2017 static const struct dev_pm_ops rk_hdptx_phy_pm_ops = {
2018 RUNTIME_PM_OPS(rk_hdptx_phy_runtime_suspend,
2019 rk_hdptx_phy_runtime_resume, NULL)
2020 };
2021
2022 static const struct rk_hdptx_phy_cfg rk3576_hdptx_phy_cfgs = {
2023 .num_phys = 1,
2024 .phy_ids = {
2025 0x2b000000,
2026 },
2027 };
2028
2029 static const struct rk_hdptx_phy_cfg rk3588_hdptx_phy_cfgs = {
2030 .num_phys = 2,
2031 .phy_ids = {
2032 0xfed60000,
2033 0xfed70000,
2034 },
2035 };
2036
2037 static const struct of_device_id rk_hdptx_phy_of_match[] = {
2038 {
2039 .compatible = "rockchip,rk3576-hdptx-phy",
2040 .data = &rk3576_hdptx_phy_cfgs
2041 },
2042 {
2043 .compatible = "rockchip,rk3588-hdptx-phy",
2044 .data = &rk3588_hdptx_phy_cfgs
2045 },
2046 {}
2047 };
2048 MODULE_DEVICE_TABLE(of, rk_hdptx_phy_of_match);
2049
2050 static struct platform_driver rk_hdptx_phy_driver = {
2051 .probe = rk_hdptx_phy_probe,
2052 .driver = {
2053 .name = "rockchip-hdptx-phy",
2054 .pm = &rk_hdptx_phy_pm_ops,
2055 .of_match_table = rk_hdptx_phy_of_match,
2056 },
2057 };
2058 module_platform_driver(rk_hdptx_phy_driver);
2059
2060 MODULE_AUTHOR("Algea Cao <[email protected]>");
2061 MODULE_AUTHOR("Cristian Ciocaltea <[email protected]>");
2062 MODULE_AUTHOR("Damon Ding <[email protected]>");
2063 MODULE_DESCRIPTION("Samsung HDMI/eDP Transmitter Combo PHY Driver");
2064 MODULE_LICENSE("GPL");
2065