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Searched refs:RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7129 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x00000000 macro
H A Dgfx_7_2_sh_mask.h7834 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 macro
H A Dgfx_8_0_sh_mask.h8736 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 macro
H A Dgfx_8_1_sh_mask.h9288 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT 0x0 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h23045 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT … macro
H A Dgc_9_1_sh_mask.h24332 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT … macro
H A Dgc_9_2_1_sh_mask.h24383 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT … macro
H A Dgc_9_4_3_sh_mask.h26640 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT … macro
H A Dgc_9_4_2_sh_mask.h21836 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT … macro
H A Dgc_11_5_0_sh_mask.h29961 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT … macro
H A Dgc_11_0_0_sh_mask.h34333 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT … macro
H A Dgc_12_0_0_sh_mask.h20067 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT … macro
H A Dgc_10_1_0_sh_mask.h33492 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT … macro
H A Dgc_11_0_3_sh_mask.h37576 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT … macro
H A Dgc_10_3_0_sh_mask.h32513 #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL__SHIFT … macro