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Searched refs:RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK (Results 1 – 13 of 13) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_sh_mask.h8705 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x10 macro
H A Dgfx_8_1_sh_mask.h9255 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK 0x10 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h23023 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK … macro
H A Dgc_9_1_sh_mask.h24310 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK … macro
H A Dgc_9_2_1_sh_mask.h24361 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK … macro
H A Dgc_9_4_3_sh_mask.h26619 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK … macro
H A Dgc_9_4_2_sh_mask.h21815 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK … macro
H A Dgc_11_5_0_sh_mask.h31553 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK … macro
H A Dgc_11_0_0_sh_mask.h36086 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK … macro
H A Dgc_12_0_0_sh_mask.h21692 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK … macro
H A Dgc_10_1_0_sh_mask.h34763 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK … macro
H A Dgc_11_0_3_sh_mask.h39424 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK … macro
H A Dgc_10_3_0_sh_mask.h34009 #define RLC_GPM_STAT__GFX_PIPELINE_POWER_STATUS_MASK … macro