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Searched refs:RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK (Results 1 – 23 of 23) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c2644 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v9_4_3_xcc_update_coarse_grain_clock_gating()
2657 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); in gfx_v9_4_3_xcc_update_coarse_grain_clock_gating()
2758 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) in gfx_v9_4_3_get_clockgating_state()
H A Dgfx_v8_0.c5439 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) in gfx_v8_0_get_clockgating_state()
5732 data |= RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v8_0_update_coarse_grain_clock_gating()
5740 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v8_0_update_coarse_grain_clock_gating()
5781 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); in gfx_v8_0_update_coarse_grain_clock_gating()
H A Dgfx_v6_0.c2562 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v6_0_enable_cgcg()
2571 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); in gfx_v6_0_enable_cgcg()
H A Dgfx_v12_0.c3909 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v12_0_update_coarse_grain_clock_gating()
3968 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v12_0_update_coarse_grain_clock_gating()
4137 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) in gfx_v12_0_get_clockgating_state()
H A Dgfx_v7_0.c3510 data |= RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v7_0_enable_cgcg()
3522 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); in gfx_v7_0_enable_cgcg()
H A Dgfx_v11_0.c5265 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v11_0_update_coarse_grain_clock_gating()
5324 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v11_0_update_coarse_grain_clock_gating()
5556 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) in gfx_v11_0_get_clockgating_state()
H A Dgfx_v9_0.c5085 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v9_0_update_coarse_grain_clock_gating()
5098 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK); in gfx_v9_0_update_coarse_grain_clock_gating()
5296 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) in gfx_v9_0_get_clockgating_state()
H A Dgfx_v10_0.c8055 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v10_0_update_coarse_grain_clock_gating()
8074 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; in gfx_v10_0_update_coarse_grain_clock_gating()
8483 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) in gfx_v10_0_get_clockgating_state()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7066 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x00000002L macro
H A Dgfx_7_2_sh_mask.h7889 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2 macro
H A Dgfx_8_0_sh_mask.h8807 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2 macro
H A Dgfx_8_1_sh_mask.h9357 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK 0x2 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h23128 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK … macro
H A Dgc_9_1_sh_mask.h24415 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK … macro
H A Dgc_9_2_1_sh_mask.h24476 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK … macro
H A Dgc_9_4_3_sh_mask.h26737 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK … macro
H A Dgc_9_4_2_sh_mask.h21925 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK … macro
H A Dgc_11_5_0_sh_mask.h30071 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK … macro
H A Dgc_11_0_0_sh_mask.h34443 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK … macro
H A Dgc_12_0_0_sh_mask.h20175 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK … macro
H A Dgc_10_1_0_sh_mask.h33585 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK … macro
H A Dgc_11_0_3_sh_mask.h37736 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK … macro
H A Dgc_10_3_0_sh_mask.h32590 #define RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK … macro