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Searched refs:RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK (Results 1 – 17 of 17) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c3901 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; in gfx_v12_0_update_coarse_grain_clock_gating()
H A Dgfx_v11_0.c5257 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; in gfx_v11_0_update_coarse_grain_clock_gating()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h7062 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x0000ff00L macro
H A Dgfx_7_2_sh_mask.h7893 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00 macro
H A Dgfx_8_0_sh_mask.h8811 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00 macro
H A Dgfx_8_1_sh_mask.h9361 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK 0x7ffff00 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h23130 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK … macro
H A Dgc_9_1_sh_mask.h24417 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK … macro
H A Dgc_9_2_1_sh_mask.h24478 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK … macro
H A Dgc_9_4_3_sh_mask.h26739 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK … macro
H A Dgc_9_4_2_sh_mask.h21927 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK … macro
H A Dgc_11_5_0_sh_mask.h30073 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK … macro
H A Dgc_11_0_0_sh_mask.h34445 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK … macro
H A Dgc_12_0_0_sh_mask.h20177 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK … macro
H A Dgc_10_1_0_sh_mask.h33587 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK … macro
H A Dgc_11_0_3_sh_mask.h37738 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK … macro
H A Dgc_10_3_0_sh_mask.h32592 #define RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK … macro