Searched refs:RIP_REL_REF (Results 1 – 7 of 7) sorted by relevance
82 RIP_REL_REF(__pgtable_l5_enabled) = 1; in check_la57_support()83 RIP_REL_REF(pgdir_shift) = 48; in check_la57_support()84 RIP_REL_REF(ptrs_per_p4d) = 512; in check_la57_support()86 RIP_REL_REF(vmalloc_base) = __VMALLOC_BASE_L5; in check_la57_support()87 RIP_REL_REF(vmemmap_base) = __VMEMMAP_BASE_L5; in check_la57_support()170 RIP_REL_REF(phys_base) = load_delta; in __startup_64()184 pgd = &RIP_REL_REF(early_top_pgt)->pgd; in __startup_64()209 RIP_REL_REF(next_early_pgt) = 2; in __startup_64()235 pmd_entry &= RIP_REL_REF(__supported_pte_mask); in __startup_64()261 pmd = &RIP_REL_REF(level2_kernel_pgt)->pmd; in __startup_64()[all …]
303 RIP_REL_REF(sev_status) & MSR_AMD64_SEV_ENABLED) in sme_encrypt_kernel()321 kernel_start = (unsigned long)RIP_REL_REF(_text); in sme_encrypt_kernel()322 kernel_end = ALIGN((unsigned long)RIP_REL_REF(_end), PMD_SIZE); in sme_encrypt_kernel()348 execute_start = workarea_start = (unsigned long)RIP_REL_REF(sme_workarea); in sme_encrypt_kernel()529 RIP_REL_REF(sev_status) = msr = __rdmsr(MSR_AMD64_SEV); in sme_enable()565 RIP_REL_REF(sme_me_mask) = me_mask; in sme_enable()566 RIP_REL_REF(physical_mask) &= ~me_mask; in sme_enable()567 RIP_REL_REF(cc_vendor) = CC_VENDOR_AMD; in sme_enable()
347 ghcb->protocol_version = RIP_REL_REF(ghcb_version); in svsm_perform_ghcb_protocol()478 return &RIP_REL_REF(cpuid_table_copy); in snp_cpuid_get_table()704 if (!(leaf->fn <= RIP_REL_REF(cpuid_std_range_max) || in snp_cpuid()1227 RIP_REL_REF(cpuid_std_range_max) = fn->eax; in setup_cpuid_table()1229 RIP_REL_REF(cpuid_hyp_range_max) = fn->eax; in setup_cpuid_table()1231 RIP_REL_REF(cpuid_ext_range_max) = fn->eax; in setup_cpuid_table()1303 if (RIP_REL_REF(snp_vmpl)) { in pvalidate_4k_page()1684 if (!rmpadjust((unsigned long)&RIP_REL_REF(boot_ghcb_page), RMP_PG_SIZE_4K, 1)) in svsm_setup_ca()1701 RIP_REL_REF(snp_vmpl) = secrets_page->svsm_guest_vmpl; in svsm_setup_ca()1716 RIP_REL_REF(boot_svsm_caa) = (struct svsm_ca *)caa; in svsm_setup_ca()[all …]
611 if (RIP_REL_REF(sev_cfg).use_cas) in svsm_get_caa()614 return RIP_REL_REF(boot_svsm_caa); in svsm_get_caa()624 if (RIP_REL_REF(sev_cfg).use_cas) in svsm_get_caa_pa()627 return RIP_REL_REF(boot_svsm_caa_pa); in svsm_get_caa_pa()673 if (RIP_REL_REF(sev_cfg).ghcbs_initialized) in svsm_perform_call_protocol()675 else if (RIP_REL_REF(boot_ghcb)) in svsm_perform_call_protocol()676 ghcb = RIP_REL_REF(boot_ghcb); in svsm_perform_call_protocol()685 if (RIP_REL_REF(sev_cfg).ghcbs_initialized) in svsm_perform_call_protocol()2478 pa = (u64)&RIP_REL_REF(boot_svsm_ca_page); in svsm_setup()2495 RIP_REL_REF(boot_svsm_caa) = (struct svsm_ca *)pa; in svsm_setup()[all …]
124 #define RIP_REL_REF(var) (*(typeof(&(var)))rip_rel_ptr(&(var))) macro126 #define RIP_REL_REF(var) (var) macro
25 RIP_REL_REF(cc_mask) = mask; in cc_set_mask()
64 return RIP_REL_REF(sme_me_mask); in sme_get_me_mask()