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Searched refs:RING_PSMI_CTL (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/xe/
H A Dxe_wa.c325 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
334 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
343 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
628 XE_RTP_ACTIONS(SET(RING_PSMI_CTL(0), RC_SEMA_IDLE_MSG_DISABLE,
H A Dxe_hw_engine.c444 XE_RTP_ACTIONS(CLR(RING_PSMI_CTL(0), in hw_engine_setup_default_state()
/linux-6.15/drivers/gpu/drm/i915/gt/
H A Dintel_ring_submission.c760 RING_PSMI_CTL(signaller->mmio_base)); in mi_set_context()
813 last_reg = RING_PSMI_CTL(signaller->mmio_base); in mi_set_context()
1047 intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE), in gen6_bsd_submit_request()
1055 RING_PSMI_CTL(GEN6_BSD_RING_BASE), in gen6_bsd_submit_request()
1068 intel_uncore_write_fw(uncore, RING_PSMI_CTL(GEN6_BSD_RING_BASE), in gen6_bsd_submit_request()
H A Dintel_engine_regs.h47 #define RING_PSMI_CTL(base) _MMIO((base) + 0x50) macro
H A Dintel_workarounds.c2304 RING_PSMI_CTL(RENDER_RING_BASE), in rcs_engine_wa_init()
/linux-6.15/drivers/gpu/drm/xe/regs/
H A Dxe_engine_regs.h63 #define RING_PSMI_CTL(base) XE_REG((base) + 0x50, XE_REG_OPTION_MASKED) macro
/linux-6.15/drivers/gpu/drm/i915/
H A Dintel_clock_gating.c444 intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE), in bdw_init_clock_gating()
581 intel_uncore_write(&i915->uncore, RING_PSMI_CTL(RENDER_RING_BASE), in chv_init_clock_gating()
H A Dintel_gvt_mmio_table.c1123 MMIO_RING_D(RING_PSMI_CTL); in iterate_bxt_mmio()
H A Di915_gpu_error.c1231 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL); in engine_record_registers()
/linux-6.15/drivers/gpu/drm/i915/gt/uc/
H A Dintel_guc_capture.c50 { RING_PSMI_CTL(0), 0, 0, "RC PSMI" }, \