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Searched refs:REG_SET_FLD (Results 1 – 4 of 4) sorted by relevance

/linux-6.15/drivers/accel/ivpu/
H A Divpu_hw_ip.c75 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, TOP_NOC, val); in host_ss_rst_clr()
76 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, DSS_MAS, val); in host_ss_rst_clr()
77 val = REG_SET_FLD(VPU_37XX_HOST_SS_CPR_RST_CLR, MSS_MAS, val); in host_ss_rst_clr()
233 val = REG_SET_FLD(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, EN, val); in idle_gen_drive_37xx()
245 val = REG_SET_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val); in idle_gen_drive_40xx()
417 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val); in host_ss_clk_drive_40xx()
418 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val); in host_ss_clk_drive_40xx()
419 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val); in host_ss_clk_drive_40xx()
464 val = REG_SET_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val); in host_ss_rst_drive_40xx()
543 val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); in top_noc_qreqn_drive_40xx()
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H A Divpu_hw_btrs.c237 val = REG_SET_FLD(VPU_HW_BTRS_MTL_WP_REQ_CMD, SEND, val); in wp_request_mtl()
261 val = REG_SET_FLD(VPU_HW_BTRS_LNL_WP_REQ_CMD, SEND, val); in wp_request_lnl()
374 val = REG_SET_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, I3, val); in d0i3_drive_mtl()
399 val = REG_SET_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, I3, val); in d0i3_drive_lnl()
477 val = REG_SET_FLD(VPU_HW_BTRS_MTL_VPU_IP_RESET, TRIGGER, val); in ip_reset_mtl()
501 val = REG_SET_FLD(VPU_HW_BTRS_LNL_IP_RESET, TRIGGER, val); in ip_reset_lnl()
529 val = REG_SET_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, PERF_CLK, val); in ivpu_hw_btrs_profiling_freq_reg_set_lnl()
544 val = REG_SET_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, DISABLE_CLK_RELINQUISH, val); in ivpu_hw_btrs_clock_relinquish_disable_lnl()
H A Divpu_mmu.c599 val = REG_SET_FLD(IVPU_MMU_REG_CR0, CMDQEN, 0); in ivpu_mmu_reset()
620 val = REG_SET_FLD(IVPU_MMU_REG_CR0, EVTQEN, val); in ivpu_mmu_reset()
625 val = REG_SET_FLD(IVPU_MMU_REG_CR0, ATSCHK, val); in ivpu_mmu_reset()
634 val = REG_SET_FLD(IVPU_MMU_REG_CR0, SMMUEN, val); in ivpu_mmu_reset()
878 val = REG_SET_FLD(IVPU_MMU_REG_CR0, EVTQEN, val); in ivpu_mmu_evtq_set()
H A Divpu_hw_reg_io.h40 #define REG_SET_FLD(REG, FLD, val) \ macro