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Searched refs:REGV_WR64 (Results 1 – 3 of 3) sorted by relevance

/linux-6.15/drivers/accel/ivpu/
H A Divpu_hw_ip.c908 REGV_WR64(VPU_40XX_HOST_SS_VERIFICATION_ADDRESS_LO, val64); in soc_cpu_boot_40xx()
995 REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK_37XX); in ivpu_hw_ip_irq_enable()
998 REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, ICB_0_1_IRQ_MASK_40XX); in ivpu_hw_ip_irq_enable()
1005 REGV_WR64(VPU_37XX_HOST_SS_ICB_ENABLE_0, 0x0ull); in ivpu_hw_ip_irq_disable()
1008 REGV_WR64(VPU_40XX_HOST_SS_ICB_ENABLE_0, 0x0ull); in ivpu_hw_ip_irq_disable()
1058 REGV_WR64(VPU_37XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK_37XX); in ivpu_hw_ip_irq_clear()
1060 REGV_WR64(VPU_40XX_HOST_SS_ICB_CLEAR_0, ICB_0_1_IRQ_MASK_40XX); in ivpu_hw_ip_irq_clear()
H A Divpu_hw_reg_io.h27 #define REGV_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regv, (reg), (val), #reg, __func__) macro
H A Divpu_mmu.c592 REGV_WR64(IVPU_MMU_REG_STRTAB_BASE, mmu->strtab.dma_q); in ivpu_mmu_reset()
595 REGV_WR64(IVPU_MMU_REG_CMDQ_BASE, mmu->cmdq.dma_q); in ivpu_mmu_reset()
616 REGV_WR64(IVPU_MMU_REG_EVTQ_BASE, mmu->evtq.dma_q); in ivpu_mmu_reset()