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Searched refs:REGV_WR32 (Results 1 – 3 of 3) sorted by relevance

/linux-6.15/drivers/accel/ivpu/
H A Divpu_hw_ip.c79 REGV_WR32(VPU_37XX_HOST_SS_CPR_RST_CLR, val); in host_ss_rst_clr()
249 REGV_WR32(VPU_40XX_HOST_SS_AON_IDLE_GEN, val); in idle_gen_drive_40xx()
409 REGV_WR32(VPU_37XX_HOST_SS_CPR_CLK_SET, val); in host_ss_clk_drive_37xx()
426 REGV_WR32(VPU_40XX_HOST_SS_CPR_CLK_EN, val); in host_ss_clk_drive_40xx()
473 REGV_WR32(VPU_40XX_HOST_SS_CPR_RST_EN, val); in host_ss_rst_drive_40xx()
497 REGV_WR32(VPU_37XX_HOST_SS_NOC_QREQN, val); in host_ss_noc_qreqn_top_socmmio_drive_37xx()
508 REGV_WR32(VPU_40XX_HOST_SS_NOC_QREQN, val); in host_ss_noc_qreqn_top_socmmio_drive_40xx()
550 REGV_WR32(VPU_40XX_TOP_NOC_QREQN, val); in top_noc_qreqn_drive_40xx()
565 REGV_WR32(VPU_37XX_TOP_NOC_QREQN, val); in top_noc_qreqn_drive_37xx()
938 REGV_WR32(VPU_37XX_CPU_SS_TIM_WDOG_EN, 0); in wdt_disable_37xx()
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H A Divpu_mmu.c439 REGV_WR32(IVPU_MMU_REG_CR0, val); in ivpu_mmu_reg_write_cr0()
446 REGV_WR32(IVPU_MMU_REG_IRQ_CTRL, val); in ivpu_mmu_reg_write_irq_ctrl()
524 REGV_WR32(IVPU_MMU_REG_CMDQ_PROD, q->prod); in ivpu_mmu_cmdq_sync()
590 REGV_WR32(IVPU_MMU_REG_CR1, val); in ivpu_mmu_reset()
596 REGV_WR32(IVPU_MMU_REG_CMDQ_PROD, 0); in ivpu_mmu_reset()
597 REGV_WR32(IVPU_MMU_REG_CMDQ_CONS, 0); in ivpu_mmu_reset()
617 REGV_WR32(IVPU_MMU_REG_EVTQ_PROD_SEC, 0); in ivpu_mmu_reset()
618 REGV_WR32(IVPU_MMU_REG_EVTQ_CONS_SEC, 0); in ivpu_mmu_reset()
881 REGV_WR32(IVPU_MMU_REG_CR0, val); in ivpu_mmu_evtq_set()
908 REGV_WR32(IVPU_MMU_REG_EVTQ_CONS_SEC, vdev->mmu->evtq.cons); in ivpu_mmu_discard_events()
[all …]
H A Divpu_hw_reg_io.h26 #define REGV_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regv, (reg), (val), #reg, __func__) macro