Searched refs:REGV_RD32 (Results 1 – 3 of 3) sorted by relevance
84 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QREQN); in host_ss_noc_qreqn_check_37xx()94 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QREQN); in host_ss_noc_qreqn_check_40xx()140 u32 val = REGV_RD32(VPU_37XX_HOST_SS_NOC_QDENY); in host_ss_noc_qdeny_check_37xx()150 u32 val = REGV_RD32(VPU_40XX_HOST_SS_NOC_QDENY); in host_ss_noc_qdeny_check_40xx()168 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN); in top_noc_qrenqn_check_37xx()179 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN); in top_noc_qrenqn_check_40xx()540 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN); in top_noc_qreqn_drive_40xx()555 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QREQN); in top_noc_qreqn_drive_37xx()583 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QACCEPTN); in top_noc_qacceptn_check_37xx()613 u32 val = REGV_RD32(VPU_37XX_TOP_NOC_QDENY); in top_noc_qdeny_check_37xx()[all …]
311 val = REGV_RD32(IVPU_MMU_REG_IDR0); in ivpu_mmu_config_check()315 val = REGV_RD32(IVPU_MMU_REG_IDR1); in ivpu_mmu_config_check()319 val = REGV_RD32(IVPU_MMU_REG_IDR3); in ivpu_mmu_config_check()330 val = REGV_RD32(IVPU_MMU_REG_IDR5); in ivpu_mmu_config_check()530 val = REGV_RD32(IVPU_MMU_REG_CMDQ_CONS); in ivpu_mmu_cmdq_sync()865 evtq->prod = REGV_RD32(IVPU_MMU_REG_EVTQ_PROD_SEC); in ivpu_mmu_get_event()875 u32 val = REGV_RD32(IVPU_MMU_REG_CR0); in ivpu_mmu_evtq_set()907 vdev->mmu->evtq.cons = REGV_RD32(IVPU_MMU_REG_EVTQ_PROD_SEC); in ivpu_mmu_discard_events()909 vdev->mmu->evtq.prod = REGV_RD32(IVPU_MMU_REG_EVTQ_PROD_SEC); in ivpu_mmu_discard_events()990 gerror_val = REGV_RD32(IVPU_MMU_REG_GERROR); in ivpu_mmu_irq_gerr_handler()[all …]
24 #define REGV_RD32(reg) ivpu_hw_reg_rd32(vdev, vdev->regv, (reg), #reg, __func__) macro