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Searched refs:Pixel (Results 1 – 25 of 87) sorted by relevance

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/linux-6.15/Documentation/devicetree/bindings/arm/
H A Dgoogle.yaml13 ARM platforms using SoCs designed by Google branded "Tensor" used in Pixel
16 Currently upstream this is devices using "gs101" SoC which is found in Pixel
17 6, Pixel 6 Pro and Pixel 6a.
26 - Marketing name ("Pixel 6")
37 - description: Google Pixel 6 or 6 Pro (Oriole or Raven)
/linux-6.15/Documentation/devicetree/bindings/display/bridge/
H A Dfsl,imx8qxp-pxl2dpi.yaml7 title: Freescale i.MX8qxp Pixel Link to Display Pixel Interface
13 The Freescale i.MX8qxp Pixel Link to Display Pixel Interface(PXL2DPI)
H A Dfsl,imx8qxp-pixel-link.yaml7 title: Freescale i.MX8qm/qxp Display Pixel Link
13 The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard
21 The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU)
H A Dfsl,imx8qxp-pixel-combiner.yaml7 title: Freescale i.MX8qm/qxp Pixel Combiner
13 The Freescale i.MX8qm/qxp Pixel Combiner takes two output streams from a
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dqcom,gcc-msm8953.yaml28 - description: Pixel clock from DSI PHY0
30 - description: Pixel clock from DSI PHY1
H A Dqcom,gcc-msm8976.yaml29 - description: Pixel clock from DSI PHY0
31 - description: Pixel clock from DSI PHY1
H A Dqcom,sa8775p-dispcc.yaml35 - description: Pixel clock from DSI0 PHY
37 - description: Pixel clock from DSI1 PHY
H A Dqcom,sm7150-dispcc.yaml31 - description: Pixel clock from MDSS DSI PHY0
33 - description: Pixel clock from MDSS DSI PHY1
H A Dqcom,sdm845-dispcc.yaml31 - description: Pixel clock from DSI PHY0
33 - description: Pixel clock from DSI PHY1
H A Dqcom,dispcc-sm6125.yaml27 - description: Pixel clock from DSI PHY0
28 - description: Pixel clock from DSI PHY1
H A Dqcom,sm8450-dispcc.yaml32 - description: Pixel clock from DSI PHY0
34 - description: Pixel clock from DSI PHY1
H A Dqcom,sm8550-dispcc.yaml39 - description: Pixel clock from DSI PHY0
41 - description: Pixel clock from DSI PHY1
H A Dqcom,dispcc-sm8x50.yaml34 - description: Pixel clock from DSI PHY0
36 - description: Pixel clock from DSI PHY1
H A Dqcom,sm6375-dispcc.yaml30 - description: Pixel clock from DSI PHY
H A Dqcom,sm6115-dispcc.yaml28 - description: Pixel clock from DSI PHY0
H A Dqcom,sm4450-dispcc.yaml33 - description: Pixel clock from DSI PHY0
/linux-6.15/Documentation/devicetree/bindings/gpu/
H A Darm,mali-utgard.yaml75 - pp # Pixel Processor broadcast interrupt (mali-450 only)
76 - pp0 # Pixel Processor X interrupt (X from 0 to 7)
77 - ppmmu0 # Pixel Processor X MMU interrupt (X from 0 to 7)
/linux-6.15/Documentation/gpu/amdgpu/display/
H A Ddc-glossary.rst31 Bits Per Pixel
34 * PCLK: Pixel Clock
41 * PPLL: Pixel PLL
/linux-6.15/Documentation/devicetree/bindings/media/
H A Dfsl,imx6ull-pxp.yaml7 title: Freescale Pixel Pipeline
14 The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
H A Dnxp,imx8-isi.yaml15 sources. The inputs to the ISI go through Pixel Link interfaces, and their
60 Ports represent the Pixel Link inputs to the ISI. Their number and
/linux-6.15/Documentation/devicetree/bindings/display/rockchip/
H A Drockchip-vop2.yaml64 - description: Pixel clock for video port 0.
65 - description: Pixel clock for video port 1.
66 - description: Pixel clock for video port 2.
67 - description: Pixel clock for video port 3.
/linux-6.15/drivers/video/fbdev/
H A Dpxa3xx-regs.h91 #define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL)) argument
/linux-6.15/drivers/media/platform/st/stm32/
H A DKconfig34 tristate "STM32 Digital Camera Memory Interface Pixel Processor (DCMIPP) support"
44 Pixel Processor (DCMIPP) available as a v4l2 device.
/linux-6.15/drivers/media/platform/nxp/
H A DKconfig47 tristate "NXP i.MX Pixel Pipeline (PXP)"
53 The i.MX Pixel Pipeline is a memory-to-memory engine for scaling,
/linux-6.15/Documentation/devicetree/bindings/display/panel/
H A Dlg,sw43408.yaml13 This panel is used on the Pixel 3, it is a 60hz OLED panel which

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