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Searched refs:PRIV_STATE (Results 1 – 12 of 12) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdkfd/
H A Dcik_regs.h64 #define PRIV_STATE (1 << 30) macro
H A Dkfd_mqd_manager_cik.c344 PRIV_STATE | in update_mqd_hiq()
/linux-6.15/drivers/gpu/drm/radeon/
H A Dcikd.h1528 #define PRIV_STATE (1 << 30) macro
H A Dcik.c4672 PRIV_STATE | KMD_QUEUE; /* assuming kernel queue control */ in cik_cp_compute_resume()
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v11_0.c1146 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in mes_v11_0_mqd_init()
H A Dmes_v12_0.c1230 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in mes_v12_0_mqd_init()
H A Dgfx_v12_0.c2907 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); in gfx_v12_0_gfx_mqd_init()
3092 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v12_0_compute_mqd_init()
H A Dgfx_v11_0.c4023 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); in gfx_v11_0_gfx_mqd_init()
4206 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v11_0_compute_mqd_init()
H A Dgfx_v9_4_3.c1864 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v9_4_3_xcc_mqd_init()
H A Dgfx_v10_0.c6743 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); in gfx_v10_0_gfx_mqd_init()
6945 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v10_0_compute_mqd_init()
H A Dgfx_v8_0.c4483 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v8_0_mqd_init()
H A Dgfx_v9_0.c3609 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v9_0_mqd_init()