Searched refs:PPE (Results 1 – 9 of 9) sorted by relevance
34 PPE = (1 << 30), /* Prefetch/Post Enable */ enumerator106 data &= ~(PM | PPE); in sch_set_piomode()110 data |= PPE; in sch_set_piomode()
43 PPE = (1 << 2), enumerator93 control |= PPE; /* Enable prefetch/posting for disk */ in mpiix_set_piomode()
150 PPE = 0x60, /* parallel poll enable (base) */ enumerator188 cmd = PPE; in PPE_byte()
15 Processor Engine (PPE) flow table.
72 Processor Engine (PPE) flow table.
20 The third region is the PPE register base and size.
29 - description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source
18 networking hardware include PPE (packet process engine), PCS
129 reads from its PPE mailbox channel. When data has been read success-