Searched refs:PORT_BASE (Results 1 – 8 of 8) sorted by relevance
112 #define PORT_BASE (0x800) macro114 #define PHY_CFG (PORT_BASE + 0x0)126 #define PHY_CTRL (PORT_BASE + 0x14)130 #define PHY_PCN (PORT_BASE + 0x44)131 #define SL_TOUT_CFG (PORT_BASE + 0x8c)132 #define SL_CONTROL (PORT_BASE + 0x94)135 #define TX_ID_DWORD0 (PORT_BASE + 0x9c)136 #define TX_ID_DWORD1 (PORT_BASE + 0xa0)157 #define CHL_INT0 (PORT_BASE + 0x1b0)172 #define CHL_INT1 (PORT_BASE + 0x1b4)[all …]
170 #define PORT_BASE (0x2000) macro172 #define PHY_CFG (PORT_BASE + 0x0)181 #define PHY_CTRL (PORT_BASE + 0x14)185 #define SL_CFG (PORT_BASE + 0x84)186 #define PHY_PCN (PORT_BASE + 0x44)187 #define SL_TOUT_CFG (PORT_BASE + 0x8c)188 #define SL_CONTROL (PORT_BASE + 0x94)203 #define TXID_AUTO (PORT_BASE + 0xb8)223 #define CHL_INT0 (PORT_BASE + 0x1b4)234 #define CHL_INT1 (PORT_BASE + 0x1b8)[all …]
187 #define PORT_BASE (0x2000) macro188 #define PHY_CFG (PORT_BASE + 0x0)201 #define PHY_CTRL (PORT_BASE + 0x14)206 #define SERDES_CFG (PORT_BASE + 0x1c)223 #define SL_CFG (PORT_BASE + 0x84)224 #define AIP_LIMIT (PORT_BASE + 0x90)225 #define SL_CONTROL (PORT_BASE + 0x94)253 #define CHL_INT0 (PORT_BASE + 0x1b4)264 #define CHL_INT1 (PORT_BASE + 0x1b8)277 #define CHL_INT2 (PORT_BASE + 0x1bc)[all …]
487 typeflags, (uint16_t)PORT_BASE, in test_datapath()488 (uint16_t)(PORT_BASE + port_off)); in test_datapath()503 pair_udp_open(fds_udp[0], PORT_BASE); in test_datapath()504 pair_udp_open(fds_udp[1], PORT_BASE + port_off); in test_datapath()
23 #define PORT_BASE 8000 macro
229 pair_udp_open(udp_sock, PORT_BASE); in walk_v1_v2_rx()590 pair_udp_open(udp_sock, PORT_BASE); in walk_v3_rx()
70 #define PORT_BASE 0x100 macro183 writel(tmp, mmio + PORT_SCR_CTL + PORT_BASE + PORT_OFFSET * i); in ahci_ceva_setup()
58 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE) macro59 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))