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Searched refs:PORT_B (Results 1 – 25 of 31) sorted by relevance

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/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Ddisplay.c313 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= in emulate_monitor_status_change()
315 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= in emulate_monitor_status_change()
322 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= in emulate_monitor_status_change()
324 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= in emulate_monitor_status_change()
329 (PORT_B << TRANS_DDI_PORT_SHIFT) | in emulate_monitor_status_change()
360 (PORT_B << TRANS_DDI_PORT_SHIFT) | in emulate_monitor_status_change()
416 ~DPLL_CTRL2_DDI_CLK_OFF(PORT_B); in emulate_monitor_status_change()
420 DPLL_CTRL2_DDI_SEL_OVERRIDE(PORT_B); in emulate_monitor_status_change()
427 (PORT_B << TRANS_DDI_PORT_SHIFT) | in emulate_monitor_status_change()
430 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &= in emulate_monitor_status_change()
[all …]
H A Dedid.c91 port = PORT_B; in cnp_get_port_from_gmbus0()
107 port = PORT_B; in bxt_get_port_from_gmbus0()
125 port = PORT_B; in get_port_from_gmbus0()
H A Dmmio.c279 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &= in intel_vgpu_reset_mmio()
281 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |= in intel_vgpu_reset_mmio()
H A Dvgpu.c376 ret = intel_gvt_set_edid(vgpu, PORT_B); in intel_gvt_create_vgpu()
H A Dhandlers.c559 case PORT_B: in bxt_vgpu_get_dp_bitrate()
666 if (port != PORT_B && port != PORT_D) { in vgpu_update_refresh_rate()
953 calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E))
2365 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2371 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2377 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write); in init_generic_mmio_info()
2781 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_B), D_BXT, in init_bxt_mmio_info()
/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_display_device.c269 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
279 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
289 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* DVO B/C */
304 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C) /* SDVO B/C */
400 .__runtime_defaults.port_mask = BIT(PORT_B) | BIT(PORT_C), /* SDVO B/C */
830 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C)
1033 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1050 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1073 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1170 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
[all …]
H A Dintel_pch_display.c86 assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B); in assert_pch_ports_disabled()
101 assert_pch_hdmi_disabled(dev_priv, pipe, PORT_B, PCH_HDMIB); in assert_pch_ports_disabled()
171 ibx_sanitize_pch_dp_port(dev_priv, PORT_B, PCH_DP_B); in ibx_sanitize_pch_ports()
176 ibx_sanitize_pch_hdmi_port(dev_priv, PORT_B, PCH_HDMIB); in ibx_sanitize_pch_ports()
444 drm_WARN_ON(display->drm, port < PORT_B || port > PORT_D); in ilk_pch_enable()
H A Dintel_display_limits.h96 PORT_B, enumerator
H A Dintel_lpe_audio.c341 ppdata = &pdata->port[port - PORT_B]; in intel_lpe_audio_notify()
368 pdata->notify_audio_lpe(display->audio.lpe.platdev, port - PORT_B); in intel_lpe_audio_notify()
H A Dintel_dpio_phy.c174 [DPIO_CH0] = { .port = PORT_B },
197 [DPIO_CH0] = { .port = PORT_B },
665 case PORT_B: in vlv_dig_port_to_channel()
679 case PORT_B: in vlv_dig_port_to_phy()
1171 case PORT_B: in vlv_wait_port_ready()
H A Dicl_dsi.c227 port = PORT_B; in icl_dsi_frame_update()
1095 if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B))) in gen11_dsi_config_util_pin()
1516 if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_is_periodic_cmd_mode()
1528 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) in gen11_dsi_get_cmd_mode_config()
1531 else if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_get_cmd_mode_config()
1657 if (intel_dsi->ports == BIT(PORT_B)) in gen11_dsi_compute_config()
2031 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); in icl_dsi_init()
H A Dintel_audio_regs.h161 #define VLV_AUD_PORT_EN_DBG(port) _MMIO_BASE_PORT3(VLV_DISPLAY_BASE, (port) - PORT_B, \
H A Dintel_sdvo.c235 if (intel_sdvo->base.port == PORT_B) in intel_sdvo_write_sdvox()
413 #define SDVO_NAME(svdo) ((svdo)->base.port == PORT_B ? "SDVOB" : "SDVOC")
1630 if (intel_sdvo->base.port == PORT_B) in intel_sdvo_pre_enable()
2625 if (sdvo->base.port == PORT_B) in intel_sdvo_select_ddc_bus()
2648 if (sdvo->base.port == PORT_B) in intel_sdvo_select_i2c_bus()
2692 if (sdvo->base.port == PORT_B) { in intel_sdvo_get_target_addr()
2719 if (sdvo->base.port == PORT_B) in intel_sdvo_get_target_addr()
3373 return port == PORT_B; in is_sdvo_port_valid()
3375 return port == PORT_B || port == PORT_C; in is_sdvo_port_valid()
3472 if (intel_sdvo->base.port == PORT_B) in intel_sdvo_init()
H A Dg4x_hdmi.c671 return port == PORT_B || port == PORT_C; in is_hdmi_port_valid()
673 return port == PORT_B || port == PORT_C || port == PORT_D; in is_hdmi_port_valid()
H A Dintel_dsi_vbt.c93 if (intel_dsi->ports & BIT(PORT_B)) in intel_dsi_seq_port_to_port()
94 return PORT_B; in intel_dsi_seq_port_to_port()
H A Dintel_bios.c1652 enum port port_bc = DISPLAY_VER(display) >= 11 ? PORT_B : PORT_C; in parse_dsi_backlight_ports()
2348 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, in dvo_port_to_port()
2363 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, in dvo_port_to_port()
2374 [PORT_B] = { -1 }, in dvo_port_to_port()
2383 [PORT_B] = { DVO_PORT_HDMIB, DVO_PORT_DPB, -1 }, in dvo_port_to_port()
2423 return PORT_B; in dsi_dvo_port_to_port()
H A Dintel_hdmi.c2709 case PORT_B: in chv_encoder_to_ddc_pin()
2732 case PORT_B: in bxt_encoder_to_ddc_pin()
2752 case PORT_B: in cnp_encoder_to_ddc_pin()
2857 WARN_ON(encoder->port == PORT_B || encoder->port == PORT_C); in adls_encoder_to_ddc_pin()
2875 case PORT_B: in g4x_encoder_to_ddc_pin()
H A Dintel_pipe_crc.c106 case PORT_B: in i9xx_pipe_crc_auto_source()
H A Dintel_dvo.c106 .port = PORT_B,
H A Dintel_display.c7694 found = intel_sdvo_init(display, PCH_SDVOB, PORT_B); in intel_setup_outputs()
7696 g4x_hdmi_init(display, PCH_HDMIB, PORT_B); in intel_setup_outputs()
7698 g4x_dp_init(display, PCH_DP_B, PORT_B); in intel_setup_outputs()
7733 has_edp = intel_dp_is_port_edp(display, PORT_B); in intel_setup_outputs()
7734 has_port = intel_bios_is_port_present(display, PORT_B); in intel_setup_outputs()
7736 has_edp &= g4x_dp_init(display, VLV_DP_B, PORT_B); in intel_setup_outputs()
7738 g4x_hdmi_init(display, VLV_HDMIB, PORT_B); in intel_setup_outputs()
7773 found = intel_sdvo_init(display, GEN3_SDVOB, PORT_B); in intel_setup_outputs()
7777 g4x_hdmi_init(display, GEN4_HDMIB, PORT_B); in intel_setup_outputs()
7781 g4x_dp_init(display, DP_B, PORT_B); in intel_setup_outputs()
H A Dintel_display_debugfs.c869 lpsp_capable = encoder->port <= PORT_B; in i915_lpsp_capability_show()
876 lpsp_capable = encoder->port <= PORT_B; in i915_lpsp_capability_show()
H A Dintel_display_irq.c1289 PORT_A : PORT_B; in gen11_dsi_te_interrupt_handler()
1321 port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A; in gen11_dsi_te_interrupt_handler()
1714 port = PORT_B; in gen11_dsi_configure_te()
H A Dintel_display.h120 case PORT_B: in port_identifier()
/linux-6.15/drivers/staging/media/tegra-video/
H A Dcsi.h30 PORT_B, enumerator
/linux-6.15/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c494 MMIO_D(PORT_CLK_SEL(PORT_B)); in iterate_generic_mmio()
525 MMIO_D(DDI_BUF_CTL(PORT_B)); in iterate_generic_mmio()
530 MMIO_D(DP_TP_CTL(PORT_B)); in iterate_generic_mmio()
535 MMIO_D(DP_TP_STATUS(PORT_B)); in iterate_generic_mmio()
1137 MMIO_D(BXT_PHY_CTL(PORT_B)); in iterate_bxt_mmio()
1140 MMIO_D(BXT_PORT_PLL_ENABLE(PORT_B)); in iterate_bxt_mmio()

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