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Searched refs:PORT_A (Results 1 – 25 of 38) sorted by relevance

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/linux-6.15/samples/bpf/
H A Dtest_map_in_map_user.c19 #define PORT_A (map_fd[0]) macro
53 ret = bpf_map_update_elem(PORT_A, &port_key, &magic_result, BPF_ANY); in populate_map()
60 ret = bpf_map_update_elem(A_OF_PORT_A, &port_key, &PORT_A, BPF_ANY); in populate_map()
62 check_map_id(PORT_A, A_OF_PORT_A, port_key); in populate_map()
64 ret = bpf_map_update_elem(H_OF_PORT_A, &port_key, &PORT_A, BPF_NOEXIST); in populate_map()
66 check_map_id(PORT_A, H_OF_PORT_A, port_key); in populate_map()
/linux-6.15/drivers/gpu/drm/i915/display/
H A Dg4x_dp.c133 if (display->platform.ivybridge && port == PORT_A) { in intel_dp_prepare()
289 if (display->platform.ivybridge && port == PORT_A) in g4x_dp_port_enabled()
291 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) in g4x_dp_port_enabled()
356 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { in intel_dp_get_config()
397 if (port == PORT_A) { in intel_dp_get_config()
432 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { in intel_dp_link_down()
567 if (port == PORT_A) in g4x_post_disable_dp()
743 if (port == PORT_A) in g4x_pre_enable_dp()
1356 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) in g4x_dp_init()
1403 if (port == PORT_A) in g4x_dp_init()
[all …]
H A Dintel_display_device.c260 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C), /* DVO A/B/C */
830 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C)
936 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D),
1033 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1050 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1073 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1112 .__runtime_defaults.port_mask = BIT(PORT_A) |
1170 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
1235 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D_XELPD) |
1338 .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | \
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H A Dvlv_dsi.c341 intel_de_rmw(display, MIPI_CTRL(display, PORT_A), GLK_MIPIIO_RESET_RELEASED, 0); in glk_dsi_enable_io()
483 intel_de_rmw(display, VLV_MIPI_PORT_CTRL(PORT_A), 0, LP_OUTPUT_HOLD); in vlv_dsi_device_ready()
579 BXT_MIPI_PORT_CTRL(port) : VLV_MIPI_PORT_CTRL(PORT_A); in vlv_dsi_clear_device_ready()
597 if ((IS_BROXTON(dev_priv) || port == PORT_A) && in vlv_dsi_clear_device_ready()
644 if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) { in intel_dsi_port_enable()
1002 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1335 tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A)); in intel_dsi_prepare()
1337 intel_de_write(display, MIPI_CTRL(display, PORT_A), in intel_dsi_prepare()
1436 MIPI_INIT_COUNT(display, port == PORT_A ? PORT_C : PORT_A), in intel_dsi_prepare()
1968 else if (port == PORT_A) in vlv_dsi_init()
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H A Dintel_ddi.c1917 case PORT_A: in bxt_ddi_get_pll()
3383 [PORT_A] = TRANSCODER_EDP, in gen9_chicken_trans_reg_by_port()
3393 port = PORT_A; in gen9_chicken_trans_reg_by_port()
4853 if (dig_port->base.port != PORT_A) in intel_ddi_a_force_4_lanes()
4909 return HPD_PORT_A + port - PORT_A; in xelpd_hpd_pin()
4918 return HPD_PORT_A + port - PORT_A; in dg1_hpd_pin()
4960 return HPD_PORT_A + port - PORT_A; in ehl_hpd_pin()
4968 return HPD_PORT_A + port - PORT_A; in skl_hpd_pin()
5025 case PORT_A: in port_strap_detected()
5379 if (port == PORT_A) in intel_ddi_init()
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H A Dintel_display_limits.h95 PORT_A = 0, enumerator
H A Dintel_bios.c1664 panel->vbt.dsi.bl_ports = BIT(PORT_A); in parse_dsi_backlight_ports()
1680 panel->vbt.dsi.cabc_ports = BIT(PORT_A); in parse_dsi_backlight_ports()
1688 BIT(PORT_A) | BIT(port_bc); in parse_dsi_backlight_ports()
2326 for (port = PORT_A; port < n_ports; port++) { in __dvo_port_to_port()
2347 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, in dvo_port_to_port()
2362 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, in dvo_port_to_port()
2373 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, in dvo_port_to_port()
2382 [PORT_A] = { DVO_PORT_HDMIA, DVO_PORT_DPA, -1 }, in dvo_port_to_port()
2420 return PORT_A; in dsi_dvo_port_to_port()
2938 if (port != PORT_A && port != PORT_E) in init_vbt_missing_defaults()
[all …]
H A Dicl_dsi.c96 if (port == PORT_A) in dsi_port_to_transcoder()
225 port = PORT_A; in icl_dsi_frame_update()
395 port == PORT_A ? in get_dsi_io_power_domains()
1392 port == PORT_A ? in gen11_dsi_disable_io_power()
1528 if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A))) in gen11_dsi_get_cmd_mode_config()
2031 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B); in icl_dsi_init()
H A Dintel_display.h118 case PORT_A: in port_identifier()
229 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++)
H A Dintel_combo_phy.c163 bool ddi_a_present = intel_bios_is_port_present(display, PORT_A); in ehl_vbt_ddi_d_present()
H A Dintel_display_power.c2357 .port_start = PORT_A,
2373 .port_start = PORT_A,
2400 .port_start = PORT_A,
2427 .port_start = PORT_A,
H A Dvlv_dsi_regs.h16 #define _MIPI_PORT(port, a, c) (((port) == PORT_A) ? a : c) /* ports A and C only */
H A Dintel_cx0_phy_regs.h33 (port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A)
H A Dintel_dpio_phy.c184 [DPIO_CH0] = { .port = PORT_A },
207 [DPIO_CH0] = { .port = PORT_A },
H A Dintel_display_irq.c1289 PORT_A : PORT_B; in gen11_dsi_te_interrupt_handler()
1290 dsi_trans = (port == PORT_A) ? TRANSCODER_DSI_0 : TRANSCODER_DSI_1; in gen11_dsi_te_interrupt_handler()
1321 port = (te_trigger & DSI1_TE) ? PORT_B : PORT_A; in gen11_dsi_te_interrupt_handler()
1716 port = PORT_A; in gen11_dsi_configure_te()
H A Dintel_dvo.c84 .port = PORT_A,
H A Dvlv_dsi_pll.c191 if (intel_dsi->ports & (1 << PORT_A)) in vlv_dsi_pll_compute()
H A Dintel_audio.c620 if (drm_WARN_ON(display->drm, port == PORT_A)) in ibx_audio_codec_disable()
656 if (drm_WARN_ON(display->drm, port == PORT_A)) in ibx_audio_codec_enable()
H A Dintel_pch_refclk.c516 if (encoder->port == PORT_A) in ilk_init_pch_refclk()
/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Ddisplay.c217 for (port = PORT_A; port <= PORT_C; port++) { in emulate_monitor_status_change()
277 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { in emulate_monitor_status_change()
283 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= in emulate_monitor_status_change()
285 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= in emulate_monitor_status_change()
288 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |= in emulate_monitor_status_change()
292 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= in emulate_monitor_status_change()
294 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &= in emulate_monitor_status_change()
500 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { in emulate_monitor_status_change()
507 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED; in emulate_monitor_status_change()
707 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) { in intel_vgpu_emulate_hotplug()
H A Dmmio.c274 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &= in intel_vgpu_reset_mmio()
276 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |= in intel_vgpu_reset_mmio()
H A Dhandlers.c555 case PORT_A: in bxt_vgpu_get_dp_bitrate()
953 calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E))
1174 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
2364 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2370 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2376 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write); in init_generic_mmio_info()
2779 MMIO_DH(BXT_PORT_PLL_ENABLE(PORT_A), D_BXT, in init_bxt_mmio_info()
/linux-6.15/drivers/staging/media/tegra-video/
H A Dcsi.h29 PORT_A = 0, enumerator
H A Dtegra210.c1016 val = ((portno & 1) == PORT_A) ? in tegra210_csi_port_start_streaming()
1109 val = ((portno & 1) == PORT_A) ? in tegra210_csi_port_stop_streaming()
/linux-6.15/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c493 MMIO_D(PORT_CLK_SEL(PORT_A)); in iterate_generic_mmio()
524 MMIO_D(DDI_BUF_CTL(PORT_A)); in iterate_generic_mmio()
529 MMIO_D(DP_TP_CTL(PORT_A)); in iterate_generic_mmio()
534 MMIO_D(DP_TP_STATUS(PORT_A)); in iterate_generic_mmio()
1136 MMIO_D(BXT_PHY_CTL(PORT_A)); in iterate_bxt_mmio()
1139 MMIO_D(BXT_PORT_PLL_ENABLE(PORT_A)); in iterate_bxt_mmio()

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