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Searched refs:PLL_ENABLE (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/phy/ti/
H A Dphy-am654-serdes.c188 PLL_ENABLE, enumerator
229 [PLL_ENABLE] = REG_FIELD(WIZ_PLL_CTRL, 29, 31),
251 ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_ENABLE_STATE); in serdes_am654_enable_pll()
264 ret = regmap_field_write(phy->fields[PLL_ENABLE], PLL_DISABLE_STATE); in serdes_am654_disable_pll()
/linux-6.15/drivers/clk/spear/
H A Dclk-vco-pll.c47 #define PLL_ENABLE 2 macro
312 parent_name, 0, mode_reg, PLL_ENABLE, 0, lock); in clk_register_vco_pll()
/linux-6.15/sound/soc/codecs/
H A Dtlv320aic3x.c1086 snd_soc_component_update_bits(component, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0); in aic3x_hw_params()
1092 PLL_ENABLE, PLL_ENABLE); in aic3x_hw_params()
1448 PLL_ENABLE, PLL_ENABLE); in aic3x_set_bias_level()
1458 PLL_ENABLE, 0); in aic3x_set_bias_level()
H A Dtlv320aic3x.h223 #define PLL_ENABLE 0x80 macro
/linux-6.15/drivers/clk/tegra/
H A Dclk-tegra210.c322 #define PLL_ENABLE (1 << 30) macro
838 if (val & PLL_ENABLE) { in tegra210_plla_set_defaults()
891 PLL_ENABLE) { in tegra210_plld_set_defaults()
944 if (val & PLL_ENABLE) { in plldss_defaults()
1063 if (val & PLL_ENABLE) { in tegra210_pllre_set_defaults()
1188 if (readl_relaxed(clk_base + pllx->params->base_reg) & PLL_ENABLE) { in tegra210_pllx_set_defaults()
1241 if (val & PLL_ENABLE) { in tegra210_pllmb_set_defaults()
1302 if (val & PLL_ENABLE) { in tegra210_pllp_set_defaults()
1365 if (val & PLL_ENABLE) { in tegra210_pllu_set_defaults()
2923 reg |= PLL_ENABLE; in tegra210_enable_pllu()
[all …]
/linux-6.15/drivers/clk/imx/
H A Dclk-imx6q.c389 #define PLL_ENABLE BIT(13) macro
417 reg &= ~PLL_ENABLE; in disable_anatop_clocks()
/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.c3562 if (!(val & PLL_ENABLE)) in mg_pll_get_hw_state()
3627 if (!(val & PLL_ENABLE)) in dkl_pll_get_hw_state()
3699 if (!(val & PLL_ENABLE)) in icl_pll_get_hw_state()
3928 intel_de_rmw(display, enable_reg, 0, PLL_ENABLE); in icl_pll_enable()
4041 intel_de_rmw(display, enable_reg, PLL_ENABLE, 0); in icl_pll_disable()
H A Dintel_snps_phy.c1847 intel_de_rmw(display, enable_reg, 0, PLL_ENABLE); in intel_mpllb_enable()
1892 intel_de_rmw(display, enable_reg, PLL_ENABLE, 0); in intel_mpllb_disable()
/linux-6.15/drivers/gpu/drm/i915/
H A Di915_reg.h3955 #define PLL_ENABLE REG_BIT(31) macro