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Searched refs:PIPE_C (Results 1 – 25 of 25) sorted by relevance

/linux-6.15/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c224 MMIO_D(SPRCTL(PIPE_C)); in iterate_generic_mmio()
225 MMIO_D(SPRLINOFF(PIPE_C)); in iterate_generic_mmio()
226 MMIO_D(SPRSTRIDE(PIPE_C)); in iterate_generic_mmio()
227 MMIO_D(SPRPOS(PIPE_C)); in iterate_generic_mmio()
228 MMIO_D(SPRSIZE(PIPE_C)); in iterate_generic_mmio()
229 MMIO_D(SPRKEYVAL(PIPE_C)); in iterate_generic_mmio()
230 MMIO_D(SPRKEYMSK(PIPE_C)); in iterate_generic_mmio()
231 MMIO_D(SPRSURF(PIPE_C)); in iterate_generic_mmio()
232 MMIO_D(SPRKEYMAX(PIPE_C)); in iterate_generic_mmio()
234 MMIO_D(SPRSCALE(PIPE_C)); in iterate_generic_mmio()
[all …]
/linux-6.15/drivers/gpu/drm/i915/display/
H A Dskl_watermark.c903 [PIPE_C] = BIT(DBUF_S2),
910 [PIPE_C] = BIT(DBUF_S2),
917 [PIPE_C] = BIT(DBUF_S2),
925 [PIPE_C] = BIT(DBUF_S2),
973 [PIPE_C] = BIT(DBUF_S2),
980 [PIPE_C] = BIT(DBUF_S2),
988 [PIPE_C] = BIT(DBUF_S2),
1022 [PIPE_C] = BIT(DBUF_S1),
1030 [PIPE_C] = BIT(DBUF_S2),
1038 [PIPE_C] = BIT(DBUF_S2),
[all …]
H A Dintel_display_limits.h19 PIPE_C, enumerator
36 TRANSCODER_C = PIPE_C,
H A Dintel_display_device.c180 [PIPE_C] = CHV_CURSOR_C_OFFSET, \
187 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
194 [PIPE_C] = IVB_CURSOR_C_OFFSET, \
501 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
992 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
1159 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
1337 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
1739 display_runtime->num_scalers[PIPE_C] = 1; in __intel_display_device_info_runtime_init()
1763 display_runtime->num_sprites[PIPE_C] = 1; in __intel_display_device_info_runtime_init()
1800 display_runtime->pipe_mask &= ~BIT(PIPE_C); in __intel_display_device_info_runtime_init()
[all …]
H A Dintel_display_power_map.c150 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
394 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
473 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
576 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
789 .irq_pipe_mask = BIT(PIPE_C),
940 .irq_pipe_mask = BIT(PIPE_C),
1083 .irq_pipe_mask = BIT(PIPE_C),
1178 .irq_pipe_mask = BIT(PIPE_C),
1352 .irq_pipe_mask = BIT(PIPE_C),
1509 .irq_pipe_mask = BIT(PIPE_C),
[all …]
H A Dintel_fdi.c148 crtc = intel_crtc_for_pipe(display, PIPE_C); in intel_fdi_add_affected_crtcs()
225 other_crtc = intel_crtc_for_pipe(display, PIPE_C); in ilk_check_fdi_lanes()
238 case PIPE_C: in ilk_check_fdi_lanes()
427 intel_de_read(display, FDI_RX_CTL(PIPE_C)) & in cpt_set_fdi_bc_bifurcation()
455 case PIPE_C: in ivb_update_fdi_bc_bifurcation()
H A Di9xx_wm.c296 case PIPE_C: in vlv_get_fifo_size()
874 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) | in vlv_write_wm_values()
875 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE)); in vlv_write_wm_values()
877 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) | in vlv_write_wm_values()
878 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC)); in vlv_write_wm_values()
1754 wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1; in _vlv_compute_pipe_wm()
1925 case PIPE_C: in vlv_atomic_update_fifo()
3367 if (dirty & WM_DIRTY_PIPE(PIPE_C)) in ilk_write_wm_values()
3725 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF); in vlv_read_wm_values()
3729 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC); in vlv_read_wm_values()
[all …]
H A Dintel_pipe_crc.c183 case PIPE_C: in vlv_pipe_crc_ctl_reg()
244 case PIPE_C: in vlv_undo_pipe_scramble_reset()
H A Dintel_dpio_phy.c696 case PIPE_C: in vlv_pipe_to_phy()
708 case PIPE_C: in vlv_pipe_to_channel()
H A Dintel_display_irq.c564 case PIPE_C: in i9xx_pipestat_irq_ack()
734 case PIPE_C: in ivb_err_int_pipe_fault_mask()
1311 pipe = PIPE_C; in gen11_dsi_te_interrupt_handler()
1800 case PIPE_C: in vlv_dpinvgtt_pipe_fault_mask()
H A Dg4x_hdmi.c764 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_hdmi_init()
H A Dskl_universal_plane.c2451 if (DISPLAY_VER(display) == 9 && pipe == PIPE_C) in skl_plane_has_planar()
2714 return pipe != PIPE_C && in skl_plane_has_rc_ccs()
2734 return pipe != PIPE_C; in glk_plane_has_rc_ccs()
H A Dicl_dsi.c823 case PIPE_C: in gen11_dsi_configure_transcoder()
1719 *pipe = PIPE_C; in gen11_dsi_get_hw_state()
H A Dintel_dmc.c464 for (pipe = PIPE_C; pipe <= PIPE_D; pipe++) in adlp_pipedmc_clock_gating_wa()
H A Dintel_cursor.c529 if (display->platform.cherryview && pipe == PIPE_C && in i9xx_check_cursor()
H A Dg4x_dp.c1388 intel_encoder->pipe_mask = BIT(PIPE_C); in g4x_dp_init()
H A Dintel_display_power_well.c1510 assert_pll_disabled(display, PIPE_C); in chv_dpio_cmn_power_well_disable()
H A Dintel_display.c2721 (pipe == PIPE_B || pipe == PIPE_C)) in intel_set_transcoder_timings()
3408 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D); in joiner_pipes()
3410 pipes = BIT(PIPE_B) | BIT(PIPE_C); in joiner_pipes()
3734 trans_pipe = PIPE_C; in hsw_enabled_transcoders()
H A Dvlv_dsi.c997 if (drm_WARN_ON(display->drm, tmp > PIPE_C)) in intel_dsi_get_hw_state()
H A Dintel_ddi.c565 case PIPE_C: in intel_ddi_transcoder_func_reg_val_get()
842 *pipe_mask = BIT(PIPE_C); in intel_ddi_get_encoder_pipes()
/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c2303 MMIO_DH(REG_50080(PIPE_C, PLANE_PRIMARY), D_ALL, NULL, in init_generic_mmio_info()
2312 MMIO_DH(REG_50080(PIPE_C, PLANE_SPRITE0), D_ALL, NULL, in init_generic_mmio_info()
2498 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2500 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2502 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2659 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2660 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2661 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2662 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2666 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
[all …]
H A Dreg.h72 (((p) == PIPE_C) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x5008C)) : \
80 (((reg) == 0x5008C || (reg) == 0x5009C) ? (PIPE_C) : \
H A Ddisplay.c63 pipe = PIPE_C; in get_edp_pipe()
642 [PIPE_C] = PIPE_C_VBLANK, in emulate_vblank_on_pipe()
646 if (pipe < PIPE_A || pipe > PIPE_C) in emulate_vblank_on_pipe()
H A Dinterrupt.c509 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_c, GEN8_DE_PIPE_ISR(PIPE_C));
H A Dcmd_parser.c1295 [4] = {PIPE_C, PLANE_A, PRIMARY_C_FLIP_DONE}, in gen8_decode_mi_display_flip()
1296 [5] = {PIPE_C, PLANE_B, SPRITE_C_FLIP_DONE}, in gen8_decode_mi_display_flip()
1355 info->pipe = PIPE_C; in skl_decode_mi_display_flip()
1370 info->pipe = PIPE_C; in skl_decode_mi_display_flip()