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Searched refs:PIPE_B (Results 1 – 25 of 34) sorted by relevance

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/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_vdsc_regs.h33 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
49 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
72 #define _ICL_DSC0_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \
75 #define _ICL_DSC1_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \
78 #define _BMG_DSC2_PPS_0(pipe) _PICK_EVEN((pipe) - PIPE_B, \
212 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
215 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
218 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
221 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
237 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
[all …]
H A Dskl_watermark.c890 [PIPE_B] = BIT(DBUF_S1),
897 [PIPE_B] = BIT(DBUF_S2),
916 [PIPE_B] = BIT(DBUF_S1),
924 [PIPE_B] = BIT(DBUF_S1),
960 [PIPE_B] = BIT(DBUF_S1),
979 [PIPE_B] = BIT(DBUF_S1),
987 [PIPE_B] = BIT(DBUF_S1),
1007 [PIPE_B] = BIT(DBUF_S1),
1015 [PIPE_B] = BIT(DBUF_S1),
1037 [PIPE_B] = BIT(DBUF_S1),
[all …]
H A Dintel_display_device.c173 [PIPE_B] = CURSOR_B_OFFSET, \
179 [PIPE_B] = CURSOR_B_OFFSET, \
186 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
193 [PIPE_B] = IVB_CURSOR_B_OFFSET, \
238 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
476 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
992 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
1159 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
1738 display_runtime->num_scalers[PIPE_B] = 2; in __intel_display_device_info_runtime_init()
1762 display_runtime->num_sprites[PIPE_B] = 2; in __intel_display_device_info_runtime_init()
[all …]
H A Dintel_display_limits.h18 PIPE_B, enumerator
35 TRANSCODER_B = PIPE_B,
H A Dintel_dpio_phy.c694 case PIPE_B: in vlv_pipe_to_phy()
710 case PIPE_B: in vlv_pipe_to_channel()
874 if (ch == DPIO_CH0 && pipe == PIPE_B) in chv_phy_pre_pll_enable()
886 if (pipe != PIPE_B) { in chv_phy_pre_pll_enable()
907 if (pipe == PIPE_B) in chv_phy_pre_pll_enable()
916 if (pipe == PIPE_B) in chv_phy_pre_pll_enable()
929 if (pipe == PIPE_B) in chv_phy_pre_pll_enable()
1038 if (pipe != PIPE_B) { in chv_phy_post_pll_disable()
1134 if (pipe == PIPE_B) in vlv_phy_pre_encoder_enable()
H A Dintel_display_power_map.c150 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
394 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
473 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
576 .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
752 .irq_pipe_mask = BIT(PIPE_B),
918 .irq_pipe_mask = BIT(PIPE_B),
1073 .irq_pipe_mask = BIT(PIPE_B),
1168 .irq_pipe_mask = BIT(PIPE_B),
1344 .irq_pipe_mask = BIT(PIPE_B),
1501 .irq_pipe_mask = BIT(PIPE_B),
[all …]
H A Di9xx_wm.c289 case PIPE_B: in vlv_get_fifo_size()
808 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in g4x_write_wm_values()
809 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | in g4x_write_wm_values()
815 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) | in g4x_write_wm_values()
859 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | in vlv_write_wm_values()
1908 case PIPE_B: in vlv_atomic_update_fifo()
3365 if (dirty & WM_DIRTY_PIPE(PIPE_B)) in ilk_write_wm_values()
3667 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); in g4x_read_wm_values()
3668 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB); in g4x_read_wm_values()
3675 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB); in g4x_read_wm_values()
[all …]
H A Dintel_fdi.c160 crtc = intel_crtc_for_pipe(display, PIPE_B); in intel_fdi_add_affected_crtcs()
171 BIT(PIPE_B)); in intel_fdi_add_affected_crtcs()
221 case PIPE_B: in ilk_check_fdi_lanes()
246 other_crtc = intel_crtc_for_pipe(display, PIPE_B); in ilk_check_fdi_lanes()
256 *pipe_to_reduce = PIPE_B; in ilk_check_fdi_lanes()
424 intel_de_read(display, FDI_RX_CTL(PIPE_B)) & in cpt_set_fdi_bc_bifurcation()
448 case PIPE_B: in ivb_update_fdi_bc_bifurcation()
H A Dintel_pipe_crc.c180 case PIPE_B: in vlv_pipe_crc_ctl_reg()
241 case PIPE_B: in vlv_undo_pipe_scramble_reset()
H A Dintel_display_power_well.c1064 if ((intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1065 i830_enable_pipe(display, PIPE_B); in i830_pipes_power_well_enable()
1071 i830_disable_pipe(display, PIPE_B); in i830_pipes_power_well_disable()
1079 intel_de_read(display, TRANSCONF(display, PIPE_B)) & TRANSCONF_ENABLE; in i830_pipes_power_well_enabled()
1378 (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0) in assert_chv_phy_status()
1507 assert_pll_disabled(display, PIPE_B); in chv_dpio_cmn_power_well_disable()
H A Dintel_pps.c44 case PIPE_B: in pps_name()
171 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
299 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
1173 if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
1265 if (pipe != PIPE_A && pipe != PIPE_B) in vlv_pps_backlight_initial_pipe()
1268 if (pipe != PIPE_A && pipe != PIPE_B) in vlv_pps_backlight_initial_pipe()
H A Dintel_display_irq.c398 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS); in i915_enable_asle_pipestat()
561 case PIPE_B: in i9xx_pipestat_irq_ack()
720 intel_pch_fifo_underrun_irq_handler(display, PIPE_B); in ibx_irq_handler()
730 case PIPE_B: in ivb_err_int_pipe_fault_mask()
854 case PIPE_B: in ilk_gtt_fault_pipe_fault_mask()
1308 pipe = PIPE_B; in gen11_dsi_te_interrupt_handler()
1795 case PIPE_B: in vlv_dpinvgtt_pipe_fault_mask()
H A Dintel_pch_display.c55 HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_dp_disabled()
75 HAS_PCH_IBX(dev_priv) && !state && port_pipe == PIPE_B, in assert_pch_hdmi_disabled()
H A Dg4x_hdmi.c404 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) { in intel_disable_hdmi()
766 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init()
H A Dicl_dsi.c820 case PIPE_B: in gen11_dsi_configure_transcoder()
1229 if (DISPLAY_VER(display) == 11 && pipe == PIPE_B) in icl_apply_kvmr_pipe_a_wa()
1575 if (DISPLAY_VER(display) == 11 && pipe == PIPE_B && in gen11_dsi_sync_state()
1716 *pipe = PIPE_B; in gen11_dsi_get_hw_state()
H A Dintel_sprite.c406 if (display->platform.cherryview && pipe == PIPE_B) in vlv_sprite_update_arm()
1634 if (display->platform.cherryview && pipe == PIPE_B) { in intel_sprite_plane_create()
1695 if (display->platform.cherryview && pipe == PIPE_B) { in intel_sprite_plane_create()
H A Dvlv_dsi.c977 TRANSCONF(dev_priv, PIPE_B)) & TRANSCONF_ENABLE; in intel_dsi_get_hw_state()
1002 *pipe = port == PORT_A ? PIPE_A : PIPE_B; in intel_dsi_get_hw_state()
1971 encoder->pipe_mask = BIT(PIPE_B); in vlv_dsi_init()
H A Dg4x_dp.c451 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { in intel_dp_link_down()
1390 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_dp_init()
H A Di9xx_plane.c1068 if (display->platform.cherryview && pipe == PIPE_B) { in intel_primary_plane_create()
1172 pipe == PIPE_B && val & DISP_MIRROR) in i9xx_get_initial_plane_config()
/linux-6.15/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c211 MMIO_D(SPRCTL(PIPE_B)); in iterate_generic_mmio()
212 MMIO_D(SPRLINOFF(PIPE_B)); in iterate_generic_mmio()
213 MMIO_D(SPRSTRIDE(PIPE_B)); in iterate_generic_mmio()
214 MMIO_D(SPRPOS(PIPE_B)); in iterate_generic_mmio()
215 MMIO_D(SPRSIZE(PIPE_B)); in iterate_generic_mmio()
216 MMIO_D(SPRKEYVAL(PIPE_B)); in iterate_generic_mmio()
217 MMIO_D(SPRKEYMSK(PIPE_B)); in iterate_generic_mmio()
218 MMIO_D(SPRSURF(PIPE_B)); in iterate_generic_mmio()
219 MMIO_D(SPRKEYMAX(PIPE_B)); in iterate_generic_mmio()
221 MMIO_D(SPRSCALE(PIPE_B)); in iterate_generic_mmio()
[all …]
H A Di915_irq.c946 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i915_irq_postinstall()
1069 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS); in i965_irq_postinstall()
/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c2300 MMIO_DH(REG_50080(PIPE_B, PLANE_PRIMARY), D_ALL, NULL, in init_generic_mmio_info()
2309 MMIO_DH(REG_50080(PIPE_B, PLANE_SPRITE0), D_ALL, NULL, in init_generic_mmio_info()
2491 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2493 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2495 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2654 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2655 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2656 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2657 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2665 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
[all …]
H A Dreg.h70 (((p) == PIPE_B) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50088)) : \
79 (((reg) == 0x50088 || (reg) == 0x50098) ? (PIPE_B) : \
H A Ddisplay.c60 pipe = PIPE_B; in get_edp_pipe()
641 [PIPE_B] = PIPE_B_VBLANK, in emulate_vblank_on_pipe()
H A Dinterrupt.c508 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(de_pipe_b, GEN8_DE_PIPE_ISR(PIPE_B));

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