Home
last modified time | relevance | path

Searched refs:PIPE_A (Results 1 – 25 of 46) sorted by relevance

12

/linux-6.15/drivers/gpu/drm/i915/
H A Dintel_gvt_mmio_table.c198 MMIO_D(SPRCTL(PIPE_A)); in iterate_generic_mmio()
199 MMIO_D(SPRLINOFF(PIPE_A)); in iterate_generic_mmio()
200 MMIO_D(SPRSTRIDE(PIPE_A)); in iterate_generic_mmio()
201 MMIO_D(SPRPOS(PIPE_A)); in iterate_generic_mmio()
202 MMIO_D(SPRSIZE(PIPE_A)); in iterate_generic_mmio()
203 MMIO_D(SPRKEYVAL(PIPE_A)); in iterate_generic_mmio()
204 MMIO_D(SPRKEYMSK(PIPE_A)); in iterate_generic_mmio()
205 MMIO_D(SPRSURF(PIPE_A)); in iterate_generic_mmio()
206 MMIO_D(SPRKEYMAX(PIPE_A)); in iterate_generic_mmio()
208 MMIO_D(SPRSCALE(PIPE_A)); in iterate_generic_mmio()
[all …]
H A Dintel_clock_gating.c317 intel_uncore_rmw(&i915->uncore, TRANS_CHICKEN1(PIPE_A), in lpt_init_clock_gating()
425 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); in bdw_init_clock_gating()
472 intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); in hsw_init_clock_gating()
/linux-6.15/drivers/gpu/drm/i915/display/
H A Dintel_pch_display.c27 (HAS_PCH_LPT_H(i915) && pch_transcoder == PIPE_A); in intel_has_pch_trancoder()
35 return PIPE_A; in intel_crtc_pch_transcoder()
126 (val & SDVO_PIPE_SEL_MASK) == SDVO_PIPE_SEL(PIPE_A)) in ibx_sanitize_pch_hdmi_port()
134 val |= SDVO_PIPE_SEL(PIPE_A); in ibx_sanitize_pch_hdmi_port()
145 (val & DP_PIPE_SEL_MASK) == DP_PIPE_SEL(PIPE_A)) in ibx_sanitize_pch_dp_port()
153 val |= DP_PIPE_SEL(PIPE_A); in ibx_sanitize_pch_dp_port()
560 assert_fdi_rx_enabled(display, PIPE_A); in lpt_enable_pch_transcoder()
562 val = intel_de_read(dev_priv, TRANS_CHICKEN2(PIPE_A)); in lpt_enable_pch_transcoder()
604 assert_pch_transcoder_disabled(dev_priv, PIPE_A); in lpt_pch_enable()
609 ilk_pch_transcoder_set_timings(crtc_state, PIPE_A); in lpt_pch_enable()
[all …]
H A Dintel_fdi.c219 case PIPE_A: in ilk_check_fdi_lanes()
446 case PIPE_A: in ivb_update_fdi_bc_bifurcation()
895 intel_de_write(display, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
906 intel_de_posting_read(display, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
945 intel_de_posting_read(display, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
951 intel_de_rmw(display, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
953 intel_de_posting_read(display, FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
976 intel_de_posting_read(display, FDI_RX_CTL(PIPE_A)); in hsw_fdi_link_train()
988 intel_de_rmw(display, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
991 intel_de_posting_read(display, FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
[all …]
H A Dintel_display_device.c167 [PIPE_A] = CURSOR_A_OFFSET, \
172 [PIPE_A] = CURSOR_A_OFFSET, \
178 [PIPE_A] = CURSOR_A_OFFSET, \
185 [PIPE_A] = CURSOR_A_OFFSET, \
192 [PIPE_A] = CURSOR_A_OFFSET, \
251 .__runtime_defaults.pipe_mask = BIT(PIPE_A), \
476 .__runtime_defaults.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
1159 BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D)
1737 display_runtime->num_scalers[PIPE_A] = 2; in __intel_display_device_info_runtime_init()
1761 display_runtime->num_sprites[PIPE_A] = 2; in __intel_display_device_info_runtime_init()
[all …]
H A Dskl_watermark.c884 [PIPE_A] = BIT(DBUF_S1),
896 [PIPE_A] = BIT(DBUF_S1),
909 [PIPE_A] = BIT(DBUF_S1),
923 [PIPE_A] = BIT(DBUF_S1),
959 [PIPE_A] = BIT(DBUF_S2),
972 [PIPE_A] = BIT(DBUF_S1),
986 [PIPE_A] = BIT(DBUF_S1),
1000 [PIPE_A] = BIT(DBUF_S1),
1014 [PIPE_A] = BIT(DBUF_S1),
1029 [PIPE_A] = BIT(DBUF_S1),
[all …]
H A Dintel_display_limits.h17 PIPE_A = 0, enumerator
34 TRANSCODER_A = PIPE_A,
H A Dg4x_hdmi.c409 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false); in intel_disable_hdmi()
410 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); in intel_disable_hdmi()
413 temp |= SDVO_ENABLE | SDVO_PIPE_SEL(PIPE_A); in intel_disable_hdmi()
427 intel_wait_for_vblank_if_active(display, PIPE_A); in intel_disable_hdmi()
428 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true); in intel_disable_hdmi()
429 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); in intel_disable_hdmi()
766 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_hdmi_init()
H A Dintel_display_reg_defs.h40 DISPLAY_INFO(display)->pipe_offsets[PIPE_A] + \
46 DISPLAY_INFO(display)->cursor_offsets[PIPE_A] + \
H A Dintel_cursor.c310 intel_de_write_fw(display, CURCNTR(display, PIPE_A), 0); in i845_cursor_update_arm()
311 intel_de_write_fw(display, CURBASE(display, PIPE_A), base); in i845_cursor_update_arm()
312 intel_de_write_fw(display, CURSIZE(display, PIPE_A), size); in i845_cursor_update_arm()
313 intel_de_write_fw(display, CURPOS(display, PIPE_A), pos); in i845_cursor_update_arm()
314 intel_de_write_fw(display, CURCNTR(display, PIPE_A), cntl); in i845_cursor_update_arm()
320 intel_de_write_fw(display, CURPOS(display, PIPE_A), pos); in i845_cursor_update_arm()
339 power_domain = POWER_DOMAIN_PIPE(PIPE_A); in i845_cursor_get_hw_state()
344 ret = intel_de_read(display, CURCNTR(display, PIPE_A)) & CURSOR_ENABLE; in i845_cursor_get_hw_state()
346 *pipe = PIPE_A; in i845_cursor_get_hw_state()
H A Di9xx_wm.c282 case PIPE_A: in vlv_get_fifo_size()
810 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); in g4x_write_wm_values()
816 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in g4x_write_wm_values()
817 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); in g4x_write_wm_values()
864 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | in vlv_write_wm_values()
1891 case PIPE_A: in vlv_atomic_update_fifo()
3363 if (dirty & WM_DIRTY_PIPE(PIPE_A)) in ilk_write_wm_values()
3669 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA); in g4x_read_wm_values()
3676 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); in g4x_read_wm_values()
3677 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA); in g4x_read_wm_values()
[all …]
H A Dg4x_dp.c271 *pipe = PIPE_A; in cpt_dp_port_selected()
456 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, false); in intel_dp_link_down()
457 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); in intel_dp_link_down()
461 intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | in intel_dp_link_down()
470 intel_wait_for_vblank_if_active(display, PIPE_A); in intel_dp_link_down()
471 intel_set_cpu_fifo_underrun_reporting(display, PIPE_A, true); in intel_dp_link_down()
472 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); in intel_dp_link_down()
1390 intel_encoder->pipe_mask = BIT(PIPE_A) | BIT(PIPE_B); in g4x_dp_init()
H A Dintel_display_power.h121 ((enum intel_display_power_domain)((pipe) - PIPE_A + POWER_DOMAIN_PIPE_A))
123 ((enum intel_display_power_domain)((pipe) - PIPE_A + POWER_DOMAIN_PIPE_PANEL_FITTER_A))
H A Dintel_crt.c257 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); in hsw_disable_crt()
286 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); in hsw_post_disable_crt()
298 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, false); in hsw_pre_pll_enable_crt()
343 intel_set_pch_fifo_underrun_reporting(display, PIPE_A, true); in hsw_enable_crt()
1076 crt->base.pipe_mask = BIT(PIPE_A); in intel_crt_init()
1142 FDI_RX_CTL(PIPE_A)) & fdi_config; in intel_crt_init()
H A Dintel_pipe_crc.c177 case PIPE_A: in vlv_pipe_crc_ctl_reg()
238 case PIPE_A: in vlv_undo_pipe_scramble_reset()
315 pipe_config->hw.active && crtc->pipe == PIPE_A && in intel_crtc_crc_setup_workarounds()
H A Dintel_dmc_regs.h22 #define PIPEDMC_ENABLE_MTL(pipe) REG_BIT(((pipe) - PIPE_A) * 4)
H A Dintel_display_power_well.c1062 if ((intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE) == 0) in i830_pipes_power_well_enable()
1063 i830_enable_pipe(display, PIPE_A); in i830_pipes_power_well_enable()
1072 i830_disable_pipe(display, PIPE_A); in i830_pipes_power_well_disable()
1078 return intel_de_read(display, TRANSCONF(display, PIPE_A)) & TRANSCONF_ENABLE && in i830_pipes_power_well_enabled()
1220 if (pipe != PIPE_A) in vlv_display_power_well_init()
1506 assert_pll_disabled(display, PIPE_A); in chv_dpio_cmn_power_well_disable()
1663 enum pipe pipe = PIPE_A; in chv_pipe_power_well_enabled()
1695 enum pipe pipe = PIPE_A; in chv_set_pipe_power_well()
H A Dintel_fifo_underrun.c140 u32 bit = (pipe == PIPE_A) ? in ilk_set_fifo_underrun_reporting()
209 u32 bit = (pch_transcoder == PIPE_A) ? in ibx_set_fifo_underrun_reporting()
H A Dintel_pps.c42 case PIPE_A: in pps_name()
171 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); in vlv_find_free_pps()
228 pipe = PIPE_A; in vlv_power_sequencer_pipe()
299 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { in vlv_initial_pps_pipe()
1173 if (drm_WARN_ON(display->drm, pipe != PIPE_A && pipe != PIPE_B)) in vlv_detach_power_sequencer()
1265 if (pipe != PIPE_A && pipe != PIPE_B) in vlv_pps_backlight_initial_pipe()
1268 if (pipe != PIPE_A && pipe != PIPE_B) in vlv_pps_backlight_initial_pipe()
1269 pipe = PIPE_A; in vlv_pps_backlight_initial_pipe()
H A Dintel_display_irq.c400 i915_enable_pipestat(dev_priv, PIPE_A, in i915_enable_asle_pipestat()
558 case PIPE_A: in i9xx_pipestat_irq_ack()
717 intel_pch_fifo_underrun_irq_handler(display, PIPE_A); in ibx_irq_handler()
726 case PIPE_A: in ivb_err_int_pipe_fault_mask()
850 case PIPE_A: in ilk_gtt_fault_pipe_fault_mask()
1305 pipe = PIPE_A; in gen11_dsi_te_interrupt_handler()
1790 case PIPE_A: in vlv_dpinvgtt_pipe_fault_mask()
1964 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS); in vlv_display_irq_postinstall()
H A Dintel_dpll.c399 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) in i9xx_dpll_get_hw_state()
1440 if (crtc->pipe != PIPE_A) in vlv_dpll()
1466 if (crtc->pipe != PIPE_A) in chv_dpll()
1977 if (pipe == PIPE_A) in vlv_prepare_pll()
1985 if (pipe == PIPE_A) in vlv_prepare_pll()
2188 if (pipe != PIPE_A) { in chv_enable_pll()
2264 if (pipe != PIPE_A) in vlv_disable_pll()
2283 if (pipe != PIPE_A) in chv_disable_pll()
H A Dhsw_ips.c190 return HAS_IPS(display) && crtc->pipe == PIPE_A; in hsw_crtc_supports_ips()
/linux-6.15/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c703 vgpu->id, pipe_name(PIPE_A), new_rate); in vgpu_update_refresh_rate()
2297 MMIO_DH(REG_50080(PIPE_A, PLANE_PRIMARY), D_ALL, NULL, in init_generic_mmio_info()
2306 MMIO_DH(REG_50080(PIPE_A, PLANE_SPRITE0), D_ALL, NULL, in init_generic_mmio_info()
2484 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2486 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2488 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL, in init_bdw_mmio_info()
2649 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2650 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2651 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
2664 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL_PLUS, NULL, NULL); in init_skl_mmio_info()
[all …]
H A Dreg.h68 (((p) == PIPE_A) ? (((q) == PLANE_PRIMARY) ? (_MMIO(0x50080)) : \
78 (((reg) == 0x50080 || (reg) == 0x50090) ? (PIPE_A) : \
H A Ddisplay.c57 pipe = PIPE_A; in get_edp_pipe()
88 pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()
640 [PIPE_A] = PIPE_A_VBLANK, in emulate_vblank_on_pipe()
646 if (pipe < PIPE_A || pipe > PIPE_C) in emulate_vblank_on_pipe()

12