| /linux-6.15/arch/arm/boot/dts/samsung/ |
| H A D | s3c64xx.dtsi | 159 clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>,
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| /linux-6.15/include/dt-bindings/clock/ |
| H A D | samsung,s3c64xx-clock.h | 85 #define PCLK_UART3 70 macro
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| H A D | exynos7-clk.h | 95 #define PCLK_UART3 3 macro
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| H A D | rk3188-cru-common.h | 87 #define PCLK_UART3 335 macro
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| H A D | rk3308-cru.h | 179 #define PCLK_UART3 200 macro
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| H A D | rockchip,rk3562-cru.h | 180 #define PCLK_UART3 168 macro
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| H A D | rk3288-cru.h | 136 #define PCLK_UART3 344 macro
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| H A D | rk3368-cru.h | 128 #define PCLK_UART3 344 macro
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| H A D | px30-cru.h | 154 #define PCLK_UART3 331 macro
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| H A D | rockchip,rk3528-cru.h | 248 #define PCLK_UART3 236 macro
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| H A D | rockchip,rk3576-cru.h | 149 #define PCLK_UART3 131 macro
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| H A D | rockchip,rv1126-cru.h | 314 #define PCLK_UART3 252 macro
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| H A D | rk3399-cru.h | 250 #define PCLK_UART3 355 macro
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| H A D | rockchip,rk3588-cru.h | 176 #define PCLK_UART3 161 macro
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| H A D | rk3568-cru.h | 356 #define PCLK_UART3 292 macro
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| /linux-6.15/drivers/clk/samsung/ |
| H A D | clk-s3c64xx.c | 240 GATE_BUS(PCLK_UART3, "pclk_uart3", "pclk", PCLK_GATE, 4),
345 ALIAS(PCLK_UART3, "s3c6400-uart.3", "uart"),
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| H A D | clk-exynos7.c | 758 GATE(PCLK_UART3, "pclk_uart3", "mout_aclk_peric1_66_user",
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| /linux-6.15/arch/arm/boot/dts/rockchip/ |
| H A D | rk3xxx.dtsi | 436 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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| /linux-6.15/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3528.dtsi | 407 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
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| /linux-6.15/drivers/clk/rockchip/ |
| H A D | clk-rk3188.c | 523 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK2928_CLKGATE_CON(8), 3, GFLAGS),
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| H A D | clk-rk3368.c | 797 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 9, GFLAGS),
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| H A D | clk-rk3288.c | 742 GATE(PCLK_UART3, "pclk_uart3", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 11, GFLAGS),
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| H A D | clk-px30.c | 848 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 7, GFLAGS),
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| H A D | clk-rk3308.c | 868 GATE(PCLK_UART3, "pclk_uart3", "pclk_bus", 0, RK3308_CLKGATE_CON(5), 13, GFLAGS),
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| /linux-6.15/arch/arm64/boot/dts/exynos/ |
| H A D | exynos7.dtsi | 316 clocks = <&clock_peric1 PCLK_UART3>,
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