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Searched refs:PCIE (Results 1 – 25 of 85) sorted by relevance

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/linux-6.15/Documentation/devicetree/bindings/phy/
H A Dairoha,en7581-pcie-phy.yaml21 - description: PCIE analog base address
22 - description: PCIE lane0 base address
23 - description: PCIE lane1 base address
24 - description: PCIE lane0 detection time base address
25 - description: PCIE lane1 detection time base address
26 - description: PCIE Rx AEQ base address
H A Dhisilicon,hi3798cv200-combphy.yaml7 title: HiSilicon STB PCIE/SATA/USB3 PHY
33 enum: [ 1, 2, 4] # SATA, PCIE, USB3
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dnbif_v6_3_1.c350 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL); in nbif_v6_3_1_program_aspm()
355 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL, data); in nbif_v6_3_1_program_aspm()
357 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL7); in nbif_v6_3_1_program_aspm()
360 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL7, data); in nbif_v6_3_1_program_aspm()
362 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3); in nbif_v6_3_1_program_aspm()
365 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL3, data); in nbif_v6_3_1_program_aspm()
399 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL4); in nbif_v6_3_1_program_aspm()
402 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL4, data); in nbif_v6_3_1_program_aspm()
422 def = data = RREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL); in nbif_v6_3_1_program_aspm()
427 WREG32_SOC15(PCIE, 0, regPCIE_LC_CNTL, data); in nbif_v6_3_1_program_aspm()
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/linux-6.15/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
H A Dpcie.c930 brcmf_dbg(PCIE, "Enter\n"); in brcmf_pcie_quick_check_isr()
971 brcmf_dbg(PCIE, "Enter\n"); in brcmf_pcie_request_irq()
1060 brcmf_dbg(PCIE, "RING !\n"); in brcmf_pcie_ring_mb_ring_bell()
1456 brcmf_dbg(PCIE, "Enter\n"); in brcmf_pcie_preinit()
1697 brcmf_dbg(PCIE, "Halt ARM.\n"); in brcmf_pcie_download_fw_nvram()
2109 brcmf_dbg(PCIE, "OTP data:\n"); in brcmf_pcie_read_otp()
2570 brcmf_dbg(PCIE, "Enter\n"); in brcmf_pcie_remove()
2618 brcmf_dbg(PCIE, "Enter\n"); in brcmf_pcie_pm_enter_D3()
2650 brcmf_dbg(PCIE, "Enter\n"); in brcmf_pcie_pm_leave_D3()
2762 brcmf_dbg(PCIE, "Enter\n"); in brcmf_pcie_register()
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H A DKconfig41 bool "PCIE bus interface support for FullMAC driver"
47 This option enables the PCIE bus interface support for Broadcom
49 use the driver for an PCIE wireless card.
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dqcom,ipq5332-gcc.yaml31 - description: PCIE 2lane PHY pipe clock source
32 - description: PCIE 2lane x1 PHY pipe clock source (For second lane)
33 - description: USB PCIE wrapper pipe clock source
34 - description: PCIE 2-lane PHY2 pipe clock source
35 - description: PCIE 2-lane PHY3 pipe clock source
H A Dqcom,sm8550-gcc.yaml26 - description: PCIE 0 Pipe clock source
27 - description: PCIE 1 Pipe clock source
28 - description: PCIE 1 Phy Auxiliary clock source
H A Dqcom,sm8650-gcc.yaml27 - description: PCIE 0 Pipe clock source
28 - description: PCIE 1 Pipe clock source
29 - description: PCIE 1 Phy Auxiliary clock source
H A Dqcom,qcs8300-gcc.yaml27 - description: PCIE 0 Pipe clock source
28 - description: PCIE 1 Pipe clock source
29 - description: PCIE Phy Auxiliary clock source
H A Dqcom,gcc-sm8450.yaml28 - description: PCIE 0 Pipe clock source (Optional clock)
29 - description: PCIE 1 Pipe clock source (Optional clock)
30 - description: PCIE 1 Phy Auxiliary clock source (Optional clock)
H A Dqcom,qdu1000-gcc.yaml27 - description: PCIE 0 Pipe clock source
28 - description: PCIE 0 Phy Auxiliary clock source
H A Dqcom,gcc-sc7280.yaml27 - description: PCIE-0 pipe clock source
28 - description: PCIE-1 pipe clock source
H A Dqcom,gcc-sdm845.yaml72 - description: PCIE 0 Pipe clock source
73 - description: PCIE 1 Pipe clock source
/linux-6.15/Documentation/admin-guide/perf/
H A Dnvidia-pmu.rst12 * PCIE
32 strongly-ordered (SO) PCIE write traffic to local/remote memory. Please see
63 PCIE device of the remote SoC.
154 The CNVLink PMU monitors traffic from GPU and PCIE device on remote sockets
172 traffic from remote GPU and PCIE devices.
193 PCIE PMU
196 The PCIE PMU monitors all read/write traffic from PCIE root ports to
235 * : PCIE : * * : PCIE : *
292 * : PCIE : * * : PCIE : *
324 | Local | PCIE PMU | SCF PMU | SCF PMU | NVLink-C2C0 |
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/linux-6.15/drivers/phy/amlogic/
H A DKconfig64 tristate "Meson G12A USB3+PCIE Combo PHY driver"
70 Enable this to support the Meson USB3 + PCIE Combo PHY found
75 tristate "Meson AXG PCIE PHY driver"
81 Enable this to support the Meson MIPI + PCIE PHY found
86 tristate "Meson AXG MIPI + PCIE analog PHY driver"
93 Enable this to support the Meson MIPI + PCIE analog PHY
/linux-6.15/Documentation/devicetree/bindings/arm/mediatek/
H A Dmediatek,mt7622-pcie-mirror.yaml7 title: MediaTek PCIE Mirror Controller for MT7622
14 The mediatek PCIE mirror provides a configuration interface for PCIE
H A Dmediatek,mt7986-wed-pcie.yaml7 title: MediaTek PCIE WED Controller for MT7986
14 The mediatek WED PCIE provides a configuration interface for PCIE
/linux-6.15/drivers/infiniband/hw/hfi1/
H A Dchip_registers.h20 #define PCIE 0 macro
584 #define PCI_CFG_MSIX0 (PCIE + 0x0000000000B0)
585 #define PCI_CFG_REG1 (PCIE + 0x000000000004)
586 #define PCI_CFG_REG11 (PCIE + 0x00000000002C)
587 #define PCIE_CFG_SPCIE1 (PCIE + 0x00000000014C)
588 #define PCIE_CFG_SPCIE2 (PCIE + 0x000000000150)
589 #define PCIE_CFG_TPH2 (PCIE + 0x000000000180)
1269 #define PCIE_CFG_REG_PL2 (PCIE + 0x000000000708)
1270 #define PCIE_CFG_REG_PL3 (PCIE + 0x00000000070C)
1273 #define PCIE_CFG_REG_PL102 (PCIE + 0x000000000898)
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/linux-6.15/drivers/net/ethernet/huawei/hinic/
H A DKconfig7 tristate "Huawei Intelligent PCIE Network Interface Card"
11 This driver supports HiNIC PCIE Ethernet cards.
/linux-6.15/drivers/phy/st/
H A Dphy-spear1310-miphy.c98 PCIE, enumerator
156 if (priv->mode == PCIE) in spear1310_miphy_init()
167 if (priv->mode == PCIE) in spear1310_miphy_exit()
197 if (priv->mode != SATA && priv->mode != PCIE) { in spear1310_miphy_xlate()
H A Dphy-spear1340-miphy.c77 PCIE, enumerator
164 else if (priv->mode == PCIE) in spear1340_miphy_init()
177 else if (priv->mode == PCIE) in spear1340_miphy_exit()
234 if (priv->mode != SATA && priv->mode != PCIE) { in spear1340_miphy_xlate()
/linux-6.15/Documentation/devicetree/bindings/pci/
H A Dstarfive,jh7110-pcie.yaml45 - description: PCIE BRIDGE reset
46 - description: PCIE CORE reset
47 - description: PCIE APB reset
/linux-6.15/Documentation/devicetree/bindings/net/wireless/
H A Dmarvell,sd8787.yaml7 title: Marvell 8787/8897/8978/8997 (sd8787/sd8897/sd8978/sd8997/pcie8997) SDIO/PCIE devices
14 This node provides properties for describing the Marvell SDIO/PCIE wireless device.
15 The node is expected to be specified as a child node to the SDIO/PCIE controller that
/linux-6.15/drivers/soc/loongson/
H A DKconfig11 The global utilities block controls PCIE device enabling, alternate
13 and PCIE, configuration of memory controller, rtc controller, lio
/linux-6.15/Documentation/translations/zh_CN/mm/
H A Dhmm.rst67 如果我们只考虑 PCIE 总线，那么设备可以访问主内存（通常通过 IOMMU）并与 CPU 缓存一
72 另一个严重的因素是带宽有限（约 32GBytes/s，PCIE 4.0 和 16 通道）。这比最快的 GPU
76 一些平台正在开发新的 I/O 总线或对 PCIE 的添加/修改以解决其中一些限制

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