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Searched refs:PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h6378 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x00001000L macro
H A Dgfx_7_2_sh_mask.h6569 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000 macro
H A Dgfx_8_0_sh_mask.h7357 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000 macro
H A Dgfx_8_1_sh_mask.h7893 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK 0x1000 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_sh_mask.h1980 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK … macro
H A Dgc_9_1_sh_mask.h1838 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK … macro
H A Dgc_9_2_1_sh_mask.h1835 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK … macro
H A Dgc_9_4_3_sh_mask.h1939 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK … macro
H A Dgc_9_4_2_sh_mask.h15362 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK … macro
H A Dgc_11_5_0_sh_mask.h20166 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK … macro
H A Dgc_11_0_0_sh_mask.h24125 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK … macro
H A Dgc_12_0_0_sh_mask.h31885 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK … macro
H A Dgc_10_1_0_sh_mask.h7548 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK … macro
H A Dgc_11_0_3_sh_mask.h26471 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK … macro
H A Dgc_10_3_0_sh_mask.h7871 #define PA_SC_ENHANCE__DISABLE_SC_PROCESS_RESET_TILE_MASK … macro